From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE1A9CA9EA0 for ; Fri, 18 Oct 2019 23:31:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81FA922474 for ; Fri, 18 Oct 2019 23:31:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="NpCxPfSm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388650AbfJRXbc (ORCPT ); Fri, 18 Oct 2019 19:31:32 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15697 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733023AbfJRXbZ (ORCPT ); Fri, 18 Oct 2019 19:31:25 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 18 Oct 2019 16:31:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 18 Oct 2019 16:31:23 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 18 Oct 2019 16:31:23 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 18 Oct 2019 23:31:22 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 18 Oct 2019 23:31:22 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 18 Oct 2019 16:31:22 -0700 From: Krishna Reddy CC: , , , , , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH v3 1/7] iommu/arm-smmu: prepare arm_smmu_flush_ops for override Date: Fri, 18 Oct 2019 16:31:26 -0700 Message-ID: <1571441492-21919-2-git-send-email-vdumpa@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571441492-21919-1-git-send-email-vdumpa@nvidia.com> References: <1571441492-21919-1-git-send-email-vdumpa@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1571441494; bh=hMkE9ZACb4SbwMYn549vbE/y19Mk47U2KnAgbKeRx6c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=NpCxPfSmbNRVMHyo8bhyoYuE3elFGxOnLaSNYVxZR3UN7ZKbLp7UXsgMBMdOfMycq 00J3awjjfInoDH9Ca6nbt9y2Qcl8XlnKri2F/ZmcVi9WtYj8qgDgxYKd/NvDs2xQwP nDzd3bqWokJ7pVRGsGT9sqBY49NQ9F5LDMNzQeles3YYc1CHJwugXN4zdQt2c9UCLj FU6zsHRfCsFwvdHkgrPdgYWE70ul8nYAgLx/lKr/+qW+H4iRc9VnOQ01Z0HEZ9uBW8 TTJPOBnM0V7+Rn09W8XBCkjhNvyu82XEP1LXD6yZtchgmDLGTGoh8shBkBuv/JVB70 vhuIrQBNyXFVA== To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove const keyword for arm_smmu_flush_ops in arm_smmu_domain and replace direct references to arm_smmu_tlb_sync* functions with arm_smmu_flush_ops->tlb_sync(). This is necessary for vendor specific implementations that need to override arm_smmu_flush_ops in part or full. Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu.c | 16 ++++++++-------- drivers/iommu/arm-smmu.h | 4 +++- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 91af695..fc0b27d 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -52,9 +52,6 @@ */ #define QCOM_DUMMY_VAL -1 -#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ -#define TLB_SPIN_COUNT 10 - #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 @@ -290,6 +287,8 @@ static void arm_smmu_tlb_sync_vmid(void *cookie) static void arm_smmu_tlb_inv_context_s1(void *cookie) { struct arm_smmu_domain *smmu_domain = cookie; + const struct arm_smmu_flush_ops *ops = smmu_domain->flush_ops; + /* * The TLBI write may be relaxed, so ensure that PTEs cleared by the * current CPU are visible beforehand. @@ -297,18 +296,19 @@ static void arm_smmu_tlb_inv_context_s1(void *cookie) wmb(); arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, ARM_SMMU_CB_S1_TLBIASID, smmu_domain->cfg.asid); - arm_smmu_tlb_sync_context(cookie); + ops->tlb_sync(cookie); } static void arm_smmu_tlb_inv_context_s2(void *cookie) { struct arm_smmu_domain *smmu_domain = cookie; struct arm_smmu_device *smmu = smmu_domain->smmu; + const struct arm_smmu_flush_ops *ops = smmu_domain->flush_ops; /* See above */ wmb(); arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); - arm_smmu_tlb_sync_global(smmu); + ops->tlb_sync(cookie); } static void arm_smmu_tlb_inv_range_s1(unsigned long iova, size_t size, @@ -410,7 +410,7 @@ static void arm_smmu_tlb_add_page(struct iommu_iotlb_gather *gather, ops->tlb_inv_range(iova, granule, granule, true, cookie); } -static const struct arm_smmu_flush_ops arm_smmu_s1_tlb_ops = { +static struct arm_smmu_flush_ops arm_smmu_s1_tlb_ops = { .tlb = { .tlb_flush_all = arm_smmu_tlb_inv_context_s1, .tlb_flush_walk = arm_smmu_tlb_inv_walk, @@ -421,7 +421,7 @@ static const struct arm_smmu_flush_ops arm_smmu_s1_tlb_ops = { .tlb_sync = arm_smmu_tlb_sync_context, }; -static const struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v2 = { +static struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v2 = { .tlb = { .tlb_flush_all = arm_smmu_tlb_inv_context_s2, .tlb_flush_walk = arm_smmu_tlb_inv_walk, @@ -432,7 +432,7 @@ static const struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v2 = { .tlb_sync = arm_smmu_tlb_sync_context, }; -static const struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v1 = { +static struct arm_smmu_flush_ops arm_smmu_s2_tlb_ops_v1 = { .tlb = { .tlb_flush_all = arm_smmu_tlb_inv_context_s2, .tlb_flush_walk = arm_smmu_tlb_inv_walk, diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index b19b6ca..b2d6c7f 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -207,6 +207,8 @@ enum arm_smmu_cbar_type { /* Maximum number of context banks per SMMU */ #define ARM_SMMU_MAX_CBS 128 +#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ +#define TLB_SPIN_COUNT 10 /* Shared driver definitions */ enum arm_smmu_arch_version { @@ -314,7 +316,7 @@ struct arm_smmu_flush_ops { struct arm_smmu_domain { struct arm_smmu_device *smmu; struct io_pgtable_ops *pgtbl_ops; - const struct arm_smmu_flush_ops *flush_ops; + struct arm_smmu_flush_ops *flush_ops; struct arm_smmu_cfg cfg; enum arm_smmu_domain_stage stage; bool non_strict; -- 2.7.4