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Mon, 21 Oct 2019 12:26:28 +0000 (GMT) From: Anvesh Salveru To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: bhelgaas@google.com, gustavo.pimentel@synopsys.com, jingoohan1@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, Anvesh Salveru , Pankaj Dubey Subject: [PATCH 1/2] dt-bindings: PCI: designware: Add binding for ZRX-DC PHY property Date: Mon, 21 Oct 2019 17:55:55 +0530 Message-Id: <1571660755-30270-1-git-send-email-anvesh.s@samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDIsWRmVeSWpSXmKPExsWy7bCmpu73xWtjDV7PYrY4u2shq8WSpgyL +UfOsVrsutvBbrHiy0x2i8u75rBZnJ13nM1i6fWLTBaLtn5ht2jde4Tdgctjzbw1jB47Z91l 91iwqdRj06pONo++LasYPbbs/8zo8XmTXAB7FJdNSmpOZllqkb5dAldG5+YDTAW7uSpOXZnJ 3sD4naOLkZNDQsBEYvftc+wgtpDAbkaJw7u8IOxPjBLf9oRD2N8YJTomisDUX/77kbmLkQso vpdR4sOUo4wQTguTxNTWf0wgVWwC2hI/j+4FmsrBISIQKXG8gRWkhlngFKPEgbPTmEFqhAUi JLYfuQ5WzyKgKnFy3WOwOK+Ai8SCnZNZIbbJSdw81wm2TUJgDZvEv8/vmCESLhI3+h9BFQlL vDq+hR3ClpJ42d8GZedL9N5dCmXXSEy528EIYdtLHLgyhwXkOGYBTYn1u/RBwswCfBK9v58w gYQlBHglOtqEIEwlibaZ1RCNEhKL59+EOsBDYu6sqyyQ8ImVuN86m2UCo8wshJkLGBlXMUqm FhTnpqcWmxYY5aWW6xUn5haX5qXrJefnbmIEpwEtrx2My875HGIU4GBU4uEtWLQ2Vog1say4 MvcQowQHs5II7x0DoBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHeSaxXY4QE0hNLUrNTUwtSi2Cy TBycUg2MmgWvP++2LXybFBemraX6xVAto8dE9/PqHTcTVXN1r15dHb1ZQ8lwTgS/3X3n7dcF GNP7zuWnfjh9eOIiT4Vv1106eyt527rsTnZws7ulmddqyiqkaTyuitI9ynlh/r/Cww9uqLct qT929dXMZUHioSp8OXkp0tVrbFXlj842tGra4qxtp6nEUpyRaKjFXFScCADVRSLP/wIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrILMWRmVeSWpSXmKPExsWy7bCSnO63xWtjDb7v0LI4u2shq8WSpgyL +UfOsVrsutvBbrHiy0x2i8u75rBZnJ13nM1i6fWLTBaLtn5ht2jde4Tdgctjzbw1jB47Z91l 91iwqdRj06pONo++LasYPbbs/8zo8XmTXAB7FJdNSmpOZllqkb5dAldG5+YDTAW7uSpOXZnJ 3sD4naOLkZNDQsBE4vLfj8xdjFwcQgK7GSXWXLjKBJGQkPiy9ysbhC0ssfLfc3YQW0igiUli 2g0LEJtNQFvi59G9QHEODhGBaIkNr4RA5jALXGKUePl4CytIXFggTOJFVwlIOYuAqsTJdY+Z QWxeAReJBTsns0KMl5O4ea6TeQIjzwJGhlWMkqkFxbnpucWGBUZ5qeV6xYm5xaV56XrJ+bmb GMEBp6W1g/HEifhDjAIcjEo8vA7T18QKsSaWFVfmHmKU4GBWEuG9Y7A2Vog3JbGyKrUoP76o NCe1+BCjNAeLkjivfP6xSCGB9MSS1OzU1ILUIpgsEwenVANjzpujN3693W2hktP2MHmRseSM bX+/BkWXl6/W5PWNi6hwLZy7fsnU0/IzW/iuGmgmr250C/vteT50zj4dg9+3Y3/3tplnh1qu DGUyiXC3j4n5eXPJ9Qe60cl3TP3Elyn7rGtm974lu2nO7CPqLO1ufu5ZBwsE6/g8RPaF3uj0 stoWrqZu+02JpTgj0VCLuag4EQACwT8sNAIAAA== X-CMS-MailID: 20191021122630epcas5p32bd92762c4304035cad5c1822d96e304 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CMS-RootMailID: 20191021122630epcas5p32bd92762c4304035cad5c1822d96e304 References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for ZRX-DC compliant PHYs. If PHY is not compliant to ZRX-DC specification, then after every 100ms link should transition to recovery state during the low power states which increases power consumption. Platforms with ZRX-DC compliant PHY can use "snps,phy-zrxdc-compliant" property in DesignWare controller DT node. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- Documentation/devicetree/bindings/pci/designware-pcie.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 78494c4050f7..9507ac38ac89 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -38,6 +38,8 @@ Optional properties: for data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers, DMA and iATU (internal Address Translation Unit) registers. +- snps,phy-zrxdc-compliant: This property is needed if phy complies with the + ZRX-DC specification. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2. -- 2.17.1