From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EADBCA9EAF for ; Mon, 28 Oct 2019 02:48:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EC3BF21850 for ; Mon, 28 Oct 2019 02:48:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730938AbfJ1Csz (ORCPT ); Sun, 27 Oct 2019 22:48:55 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:53869 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729515AbfJ1Csg (ORCPT ); Sun, 27 Oct 2019 22:48:36 -0400 X-UUID: 43c090c6865644b38579d7157eb6e64a-20191028 X-UUID: 43c090c6865644b38579d7157eb6e64a-20191028 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1817805963; Mon, 28 Oct 2019 10:48:28 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 28 Oct 2019 10:48:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 28 Oct 2019 10:48:27 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring CC: James Liao , Fan Chen , , , , , Weiyi Lu , Yong Wu Subject: [PATCH v8 11/14] soc: mediatek: Add extra sram control Date: Mon, 28 Oct 2019 10:48:15 +0800 Message-ID: <1572230898-7860-12-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1572230898-7860-1-git-send-email-weiyi.lu@mediatek.com> References: <1572230898-7860-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 584E7679CB6D35FCD8698EAF05CBB4451FAC5DACF543865D192807EC2A388ECE2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 0b5055c..992e5b3 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -57,6 +57,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) #define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) @@ -115,6 +117,8 @@ enum clk_id { * @name: The domain name. * @sta_mask: The mask for power on/off status bit. * @ctl_offs: The offset for main power control register. + * @sram_iso_ctrl: The flag to judge if the power domain need to do + * the extra sram isolation control. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. * @bus_prot_mask: The mask for single step bus protection. @@ -130,6 +134,7 @@ struct scp_domain_data { const char *name; u32 sta_mask; int ctl_offs; + bool sram_iso_ctrl; u32 sram_pdn_bits; u32 sram_pdn_ack_bits; u32 bus_prot_mask; @@ -268,6 +273,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr) return ret; } + if (scpd->data->sram_iso_ctrl) { + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + val &= ~PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + } + return 0; } @@ -277,6 +290,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) u32 pdn_ack = scpd->data->sram_pdn_ack_bits; int tmp; + if (scpd->data->sram_iso_ctrl) { + val = readl(ctl_addr); + val |= PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + val &= ~PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + } + val = readl(ctl_addr) | scpd->data->sram_pdn_bits; writel(val, ctl_addr); -- 1.8.1.1.dirty