From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37AB0CA9ECF for ; Sat, 2 Nov 2019 01:20:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1651921855 for ; Sat, 2 Nov 2019 01:20:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728415AbfKBBUv (ORCPT ); Fri, 1 Nov 2019 21:20:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:33444 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726892AbfKBBUu (ORCPT ); Fri, 1 Nov 2019 21:20:50 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 5DF9B615E4; Sat, 2 Nov 2019 01:20:50 +0000 (UTC) Received: from pacamara-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cang@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E9D8861564; Sat, 2 Nov 2019 01:20:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E9D8861564 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=pass (p=none dis=none) header.from=qti.qualcomm.com Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cang@qti.qualcomm.com From: Can Guo To: asutoshd@codeaurora.org, nguyenb@codeaurora.org, rnayak@codeaurora.org, linux-scsi@vger.kernel.org, kernel-team@android.com, saravanak@google.com, salyzyn@google.com, cang@codeaurora.org Cc: Alim Akhtar , Avri Altman , Pedro Sousa , "James E.J. Bottomley" , "Martin K. Petersen" , Stanley Chu , Bean Huo , Subhash Jadavani , Tomas Winkler , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/5] scsi: ufs: Set DBD setting in mode sense for caching mode page Date: Fri, 1 Nov 2019 18:20:27 -0700 Message-Id: <1572657631-25749-3-git-send-email-cang@qti.qualcomm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1572657631-25749-1-git-send-email-cang@qti.qualcomm.com> References: <1572657631-25749-1-git-send-email-cang@qti.qualcomm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Can Guo Host sends MODE_SENSE_10 with caching mode page, to check if the device supports the cache feature. UFS standards requires DBD field to be set to 1. Some card vendors are more strict and check the DBD field, hence respond with CHECK_CONDITION (Sense key set to ILLEGAL_REQUEST and ASC set to INVALID FIELD IN CDB). As a result of the CHECK_CONDITION response, host assumes that the device doesn't support the cache feature and doesn't send SYNCHRONIZE_CACHE commands to flush the device cache. This can result in data corruption in case of sudden power down, when there is data stored in the device cache. This patch fixes the DBD field setting in case of caching mode page. Signed-off-by: Can Guo --- drivers/scsi/ufs/ufshcd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 0026199..0a6b8f9 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -8353,6 +8353,7 @@ int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) host->max_channel = UFSHCD_MAX_CHANNEL; host->unique_id = host->host_no; host->max_cmd_len = UFS_CDB_SIZE; + host->set_dbd_for_caching = 1; hba->max_pwr_info.is_valid = false; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project