From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752503AbdK1NLf (ORCPT ); Tue, 28 Nov 2017 08:11:35 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:33457 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752260AbdK1NLd (ORCPT ); Tue, 28 Nov 2017 08:11:33 -0500 Subject: Re: [PATCH v4 0/4] fix the clock setting for SAR ADC To: Jonathan Cameron , Martin Blumenstingl References: <20171107140942.29243-1-yixun.lan@amlogic.com> <20171111003737.000038f0@huawei.com> CC: , Mark Rutland , , , Neil Armstrong , , Stephen Boyd , Michael Turquette , , Rob Herring , Xingyu Chen , Kevin Hilman , Carlo Caione , , , Jonathan Cameron , Jerome Brunet From: Yixun Lan Message-ID: <15745fd0-1af9-c7c0-8769-063f218a3d28@amlogic.com> Date: Tue, 28 Nov 2017 21:11:29 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <20171111003737.000038f0@huawei.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [58.34.187.116] X-ClientProxiedBy: mail-sh2.amlogic.com (10.18.11.6) To mail-sh2.amlogic.com (10.18.11.6) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/11/17 08:37, Jonathan Cameron wrote: > On Tue, 7 Nov 2017 22:36:00 +0100 > Martin Blumenstingl wrote: > >> Hi Yixun, >> >> On Tue, Nov 7, 2017 at 3:09 PM, Yixun Lan wrote: >>> patch [1/4]: >>> Fix wrong SARADC/SANA clock gate bit in Meson-GXBB/GXL, >>> the published datasheets[4] also has wrong description about this. >>> This patch should be explicitly merged *before* other patches. >>> >>> patch [2-4/4]: >>> Drop the "sana" clock from SAR ADC module, >> I agree with Jerome that patch 2/4 should be applied last. > > Let me know when I should take this. > > Thanks, > > Jonathan > >> when I wrote the driver I couldn't get it to work on my GXBB board >> (which unfortunately has died since then) because the clocks were >> disabled (they weren't enabled by the bootloader). people who are >> using an old .dtb would get the same problem again until the clock >> driver is merged >> >>> From the hardware perspective, the SAR ADC module doesn't >>> require "sana" clock to wrok. This should apply to all SoC, >>> including meson6,8, GXBB, GXL.. >> thank you for clarifying this! >> >>> Note: the whole patchset series has been tested at GXL-P212 board, >>> we haven't got any meson6,8 board to test, so I would appreciate >>> if someone (Martin?) could help to confirm it works there. >> I can test this on a Meson8b and a Meson8m2 board on the weekend - >> I'll let you know about the results >> >> >> Regards >> Martin >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-iio" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html > > > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic > > . > Hi Jonathan Cameron & Kevin Hilman: since the clk part patch has been applied[1], can we proceed with others? to Jonathan: I think the iio part(patch [2/4]) should be merged via your iio tree? see [2] to Kevin: could you take the DTS part? see [3], and the patch [4/4] has a rework version, see [4], to separate dt64 vs dt32 device tree. [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005472.html [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005264.html [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005265.html [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005304.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005305.html http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005306.html Yixun