From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECB45C432C0 for ; Thu, 28 Nov 2019 20:24:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B9E0321775 for ; Thu, 28 Nov 2019 20:24:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="daj/EdjY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726663AbfK1UYB (ORCPT ); Thu, 28 Nov 2019 15:24:01 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:27979 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726558AbfK1UYB (ORCPT ); Thu, 28 Nov 2019 15:24:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1574972640; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=XqTwc5ebz6tenvnG6zkONwdSyh0ZcAJ7/GPADSmX7as=; b=daj/EdjYZyauOID1QtsTH6Bw5IeoGciF4aqx6kxqUUi+1fyUlrX/ZSyUOAbs5BOVkN/24T +u4PeeZYCPhA8rgl0LCAYGQigo8Pyj96oPiYgoc5Khmbl4Fx00UqaB8jxjc2tnTcwZmOX/ ug1agBcZRNtQNttTHz4vwLWEcTecZBA= Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-55-4HYKBWAIPWOm1m0PzMr3Kw-1; Thu, 28 Nov 2019 15:23:57 -0500 Received: by mail-pl1-f199.google.com with SMTP id s7so515703plp.3 for ; Thu, 28 Nov 2019 12:23:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=GPEyz/IHgt6mAW0R3tmNHtqBX2Y5bDBhF2H/Q45W8jA=; b=sgOfOEH6Z5QeFVNW9Wd5YsbJ1rjrAybjItPg5hRSabYnpQkNLnPKp5jQ/SjgI8T0FN mYHkQx+aAhkYT99rNbOFhWgZHvm14sunscwBcMu7gHeKJQF0OgEefQVFlhGnPb9rR16I KrMZPfF/yXB/zfMCJpuIGt+y5oj9Hv5Pgaz7n2WYAseezFyNWrrLsGrjm69CuG4eE70K zOluC+1CIYopX+PKcJM7PrJQXDCi2g5YbQoYmWFJRl2Fz/8Zh5+vH7oSQu7I8OhnAKWr hXNRxjZpdCUxrY/S0dtqm1zspk++Xp6hc8X8ws40RAkWeRPEP99jXO6Vh8JDKN4QPV5d n4mA== X-Gm-Message-State: APjAAAWKeVh+NJ6geotzdDX+vdRUIvLgrvDAtpBBB2yVA+NQrJy55Xpf GCp//IWDIHvzPUKeA+2GL+bEjguFrk3WLlEchZt/Xw4KKPyq60wYtgAmhNkhXMyc8E8moY/gWDf baPps7lVMkU7b6ghr0hEY9weq X-Received: by 2002:a17:90b:3109:: with SMTP id gc9mr9966535pjb.30.1574972636141; Thu, 28 Nov 2019 12:23:56 -0800 (PST) X-Google-Smtp-Source: APXvYqwLgmQBIVDgB8JTDBBuFEwN/117Vx9qIR4Jgevr8C1kD585Wc5/+quQsfVlRjSD579x56aJyQ== X-Received: by 2002:a17:90b:3109:: with SMTP id gc9mr9966493pjb.30.1574972635767; Thu, 28 Nov 2019 12:23:55 -0800 (PST) Received: from localhost ([122.177.85.74]) by smtp.gmail.com with ESMTPSA id a15sm2778299pfh.169.2019.11.28.12.23.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2019 12:23:54 -0800 (PST) From: Bhupesh Sharma To: linux-kernel@vger.kernel.org Cc: bhsharma@redhat.com, bhupesh.linux@gmail.com, x86@kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kexec@lists.infradead.org, Boris Petkov , Ingo Molnar , Thomas Gleixner , Jonathan Corbet , James Morse , Mark Rutland , Will Deacon , Steve Capper , Catalin Marinas , Ard Biesheuvel , Michael Ellerman , Paul Mackerras , Benjamin Herrenschmidt , Dave Anderson , Kazuhito Hagio Subject: [PATCH v5 0/5] Append new variables to vmcoreinfo (TCR_EL1.T1SZ for arm64 and MAX_PHYSMEM_BITS for all archs) Date: Fri, 29 Nov 2019 01:53:36 +0530 Message-Id: <1574972621-25750-1-git-send-email-bhsharma@redhat.com> X-Mailer: git-send-email 2.7.4 X-MC-Unique: 4HYKBWAIPWOm1m0PzMr3Kw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v4: ---------------- - v4 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-November/023961.html - Addressed comments from Dave and added patches for documenting new variables appended to vmcoreinfo documentation. - Added testing report shared by Akashi for PATCH 2/5. Changes since v3: ---------------- - v3 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022590.html - Addressed comments from James and exported TCR_EL1.T1SZ in vmcoreinfo instead of PTRS_PER_PGD. - Added a new patch (via [PATCH 3/3]), which fixes a simple typo in 'Documentation/arm64/memory.rst' Changes since v2: ---------------- - v2 can be seen here: http://lists.infradead.org/pipermail/kexec/2019-March/022531.html - Protected 'MAX_PHYSMEM_BITS' vmcoreinfo variable under CONFIG_SPARSEMEM ifdef sections, as suggested by Kazu. - Updated vmcoreinfo documentation to add description about 'MAX_PHYSMEM_BITS' variable (via [PATCH 3/3]). Changes since v1: ---------------- - v1 was sent out as a single patch which can be seen here: http://lists.infradead.org/pipermail/kexec/2019-February/022411.html - v2 breaks the single patch into two independent patches: [PATCH 1/2] appends 'PTRS_PER_PGD' to vmcoreinfo for arm64 arch, whereas [PATCH 2/2] appends 'MAX_PHYSMEM_BITS' to vmcoreinfo in core kernel code = (all archs) This patchset primarily fixes the regression reported in user-space utilities like 'makedumpfile' and 'crash-utility' on arm64 architecture with the availability of 52-bit address space feature in underlying kernel. These regressions have been reported both on CPUs which don't support ARMv8.2 extensions (i.e. LVA, LPA) and are running newer kernels and also on prototype platforms (like ARMv8 FVP simulator model) which support ARMv8.2 extensions and are running newer kernels. The reason for these regressions is that right now user-space tools have no direct access to these values (since these are not exported from the kernel) and hence need to rely on a best-guess method of determining value of 'vabits_actual' and 'MAX_PHYSMEM_BITS' supported by underlying kernel. Exporting these values via vmcoreinfo will help user-land in such cases. In addition, as per suggestion from makedumpfile maintainer (Kazu), it makes more sense to append 'MAX_PHYSMEM_BITS' to vmcoreinfo in the core code itself rather than in arm64 arch-specific code, so that the user-space code for other archs can also benefit from this addition to the vmcoreinfo and use it as a standard way of determining 'SECTIONS_SHIFT' value in user-land. Cc: Boris Petkov Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Jonathan Corbet Cc: James Morse Cc: Mark Rutland Cc: Will Deacon Cc: Steve Capper Cc: Catalin Marinas Cc: Ard Biesheuvel Cc: Michael Ellerman Cc: Paul Mackerras Cc: Benjamin Herrenschmidt Cc: Dave Anderson Cc: Kazuhito Hagio Cc: x86@kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: kexec@lists.infradead.org Bhupesh Sharma (5): crash_core, vmcoreinfo: Append 'MAX_PHYSMEM_BITS' to vmcoreinfo arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Documentation/arm64: Fix a simple typo in memory.rst Documentation/vmcoreinfo: Add documentation for 'MAX_PHYSMEM_BITS' Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ' Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ Documentation/arm64/memory.rst | 2 +- arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/kernel/crash_core.c | 9 +++++++++ kernel/crash_core.c | 1 + 5 files changed, 23 insertions(+), 1 deletion(-) --=20 2.7.4