From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB6E1C34015 for ; Fri, 13 Dec 2019 20:38:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EA4C2246C0 for ; Fri, 13 Dec 2019 20:38:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727704AbfLMPFI (ORCPT ); Fri, 13 Dec 2019 10:05:08 -0500 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:27553 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726528AbfLMPFI (ORCPT ); Fri, 13 Dec 2019 10:05:08 -0500 Received-SPF: Pass (esa1.microchip.iphmx.com: domain of Claudiu.Beznea@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa1.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="Claudiu.Beznea@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com -exists:%{i}.spf.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa1.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa1.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa1.microchip.iphmx.com; dkim=none (message not signed) header.i=none; spf=Pass smtp.mailfrom=Claudiu.Beznea@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: /l3zNd7W8x5mGxD5D2YKoB1ZSgknSeaTBybraVXNXDLaHm0eK/6PWCZz5tbCMhBfosSQk99CMd sun3NtdDv8aYIoRGm4z0TPZ/CjWpJ9uiZz54nOAyE58fK2qAOiwinDmKSjahHddnQWWvvfetST ckayaBEyvavx3V+Kp+T9fDkeUaQyeJDbbtHiuZIPIrabWW6LqIRxB13GEMq5cdGQSZgwjzLScP o1lcMPyuTP/IHzWr7cWsZm8HA2xfjYrUqmWEtVoFw7TC++lzLZVf12NqSWfQmGy4T5C19yxMlF PRI= X-IronPort-AV: E=Sophos;i="5.69,309,1571727600"; d="scan'208";a="61646956" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Dec 2019 08:05:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 13 Dec 2019 08:05:06 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.85.251) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Fri, 13 Dec 2019 08:05:02 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , Claudiu Beznea Subject: [PATCH v2 0/6] fixes for atmel-hlcdc Date: Fri, 13 Dec 2019 17:04:50 +0200 Message-ID: <1576249496-4849-1-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, I have few fixes for atmel-hlcdc driver in this series as well as two reverts. Revert "drm: atmel-hlcdc: enable sys_clk during initalization." is due to the fix in in patch 2/5. Thank you, Claudiu Beznea Changes in v2: - introduce patch 3/6 - use dev_err() inpatch 4/6 - introduce patch 5/6 instead of reverting commit f6f7ad323461 ("drm/atmel-hlcdc: allow selecting a higher pixel-clock than requested") Claudiu Beznea (5): drm: atmel-hlcdc: use double rate for pixel clock only if supported drm: atmel-hlcdc: enable clock before configuring timing engine mfd: atmel-hlcdc: add struct device member to struct atmel_hlcdc_regmap mfd: atmel-hlcdc: return in case of error Revert "drm: atmel-hlcdc: enable sys_clk during initalization." Peter Rosin (1): drm: atmel-hlcdc: prefer a lower pixel-clock than requested drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 18 ++++++++++++------ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 19 +------------------ drivers/mfd/atmel-hlcdc.c | 18 ++++++++++++++---- 3 files changed, 27 insertions(+), 28 deletions(-) -- 2.7.4