From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <sre@kernel.org>,
<alexandre.belloni@bootlin.com>
Cc: <linux-pm@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH 0/2] at91-sama5d2_shdwc shutdown controller
Date: Thu, 19 Dec 2019 16:27:52 +0200 [thread overview]
Message-ID: <1576765674-22070-1-git-send-email-claudiu.beznea@microchip.com> (raw)
PMC master clock register offset is different b/w sam9x60 and
other SoCs. Since there is a need of this register offset in
shutdown procedure we need to have it per SoC. This is what
this series does.
Claudiu Beznea (2):
power: reset: at91-sama5d2_shdwc: introduce struct shdwc_reg_config
power: reset: at91-sama5d2_shdwc: use proper master clock register
offset
drivers/power/reset/at91-sama5d2_shdwc.c | 75 +++++++++++++++++++++-----------
1 file changed, 49 insertions(+), 26 deletions(-)
--
2.7.4
next reply other threads:[~2019-12-19 14:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-19 14:27 Claudiu Beznea [this message]
2019-12-19 14:27 ` [PATCH 1/2] power: reset: at91-sama5d2_shdwc: introduce struct shdwc_reg_config Claudiu Beznea
2019-12-19 14:27 ` [PATCH 2/2] power: reset: at91-sama5d2_shdwc: use proper master clock register offset Claudiu Beznea
2019-12-19 17:04 ` [PATCH 0/2] at91-sama5d2_shdwc shutdown controller Sebastian Reichel
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