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Tue, 4 Feb 2020 13:41:22 +0000 From: peng.fan@nxp.com To: shawnguo@kernel.org, s.hauer@pengutronix.de, sboyd@kernel.org, abel.vesa@nxp.com, aisheng.dong@nxp.com, leonard.crestez@nxp.com Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, ping.bai@nxp.com, Anson.Huang@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Peng Fan Subject: [PATCH 3/7] clk: imx: pfdv2: determine best parent rate Date: Tue, 4 Feb 2020 21:34:33 +0800 Message-Id: <1580823277-13644-4-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580823277-13644-1-git-send-email-peng.fan@nxp.com> References: <1580823277-13644-1-git-send-email-peng.fan@nxp.com> Content-Type: text/plain X-ClientProxiedBy: HK0PR03CA0107.apcprd03.prod.outlook.com (2603:1096:203:b0::23) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.66) by HK0PR03CA0107.apcprd03.prod.outlook.com (2603:1096:203:b0::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2686.28 via Frontend Transport; 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To get best pfd output, the i.MX7ULP Datasheet defines two best PLL rate and pfd frac. Per Datasheel All PLLs on i.MX 7ULP either have VCO base frequency of 480 MHz or 528 MHz. So when determine best rate, we also determine best parent rate which could match the requirement. For some reason the current parent might not be 480MHz or 528MHz, so we still take current parent rate as a choice. And we also enable flag CLK_SET_RATE_PARENT to let parent rate to be configured. Signed-off-by: Peng Fan --- drivers/clk/imx/clk-pfdv2.c | 50 ++++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c index 28b5f208ced9..78e1f7641aaa 100644 --- a/drivers/clk/imx/clk-pfdv2.c +++ b/drivers/clk/imx/clk-pfdv2.c @@ -101,24 +101,40 @@ static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw, static int clk_pfdv2_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - u64 tmp = req->best_parent_rate; - u64 rate = req->rate; + unsigned long parent_rates[] = { + 480000000, + 528000000, + req->best_parent_rate + }; + unsigned long best_rate = -1UL, rate = req->rate; + unsigned long best_parent_rate = req->best_parent_rate; + u64 tmp; u8 frac; + int i; + + for (i = 0; i < ARRAY_SIZE(parent_rates); i++) { + tmp = parent_rates[i]; + tmp = tmp * 18 + rate / 2; + do_div(tmp, rate); + frac = tmp; + + if (frac < 12) + frac = 12; + else if (frac > 35) + frac = 35; + + tmp = parent_rates[i]; + tmp *= 18; + do_div(tmp, frac); + + if (abs(tmp - req->rate) < abs(best_rate - req->rate)) { + best_rate = tmp; + best_parent_rate = parent_rates[i]; + } + } - tmp = tmp * 18 + rate / 2; - do_div(tmp, rate); - frac = tmp; - - if (frac < 12) - frac = 12; - else if (frac > 35) - frac = 35; - - tmp = req->best_parent_rate; - tmp *= 18; - do_div(tmp, frac); - - req->rate = tmp; + req->best_parent_rate = best_parent_rate; + req->rate = best_rate; return 0; } @@ -198,7 +214,7 @@ struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name, init.ops = &clk_pfdv2_ops; init.parent_names = &parent_name; init.num_parents = 1; - init.flags = CLK_SET_RATE_GATE; + init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; pfd->hw.init = &init; -- 2.16.4