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From: "Moger, Babu" <babu.moger@amd.com>
To: Reinette Chatre <reinette.chatre@intel.com>,
	corbet@lwn.net, tglx@linutronix.de, mingo@redhat.com,
	bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org
Cc: fenghua.yu@intel.com, hpa@zytor.com, paulmck@kernel.org,
	thuth@redhat.com, xiongwei.song@windriver.com, ardb@kernel.org,
	pawan.kumar.gupta@linux.intel.com,
	daniel.sneddon@linux.intel.com, sandipan.das@amd.com,
	kai.huang@intel.com, peterz@infradead.org,
	kan.liang@linux.intel.com, pbonzini@redhat.com,
	xin3.li@intel.com, ebiggers@google.com,
	alexandre.chartre@oracle.com, perry.yuan@amd.com,
	tan.shaopeng@fujitsu.com, james.morse@arm.com,
	tony.luck@intel.com, maciej.wieczor-retman@intel.com,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	peternewman@google.com, eranian@google.com
Subject: Re: [PATCH 6/7] x86/resctrl: Introduce interface to display SDCIAE Capacity Bit Masks
Date: Wed, 18 Sep 2024 15:19:33 -0500	[thread overview]
Message-ID: <15824c9d-b39a-43f8-b33c-787053061d70@amd.com> (raw)
In-Reply-To: <f1b98b0f-d2ab-40a3-87a0-193e67f345e0@intel.com>

Hi Reinette,

On 9/13/24 15:52, Reinette Chatre wrote:
> Hi Babu,
> 
> On 8/16/24 9:16 AM, Babu Moger wrote:
>> When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache
>> partitions identified by the highest-supported L3_MASK_n register where
>> n is the maximum CLOSID supported.
>>
>> Add the interface to display CBMs (Capacity Bit Mask) of the SDCIAE.
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
>>   arch/x86/kernel/cpu/resctrl/ctrlmondata.c |  2 +-
>>   arch/x86/kernel/cpu/resctrl/internal.h    |  1 +
>>   arch/x86/kernel/cpu/resctrl/rdtgroup.c    | 29 +++++++++++++++++++++++
>>   3 files changed, 31 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>> b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>> index 50fa1fe9a073..fc99f4d17e6c 100644
>> --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>> +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>> @@ -439,7 +439,7 @@ u32 resctrl_arch_get_config(struct rdt_resource *r,
>> struct rdt_ctrl_domain *d,
>>       return hw_dom->ctrl_val[idx];
>>   }
>>   -static void show_doms(struct seq_file *s, struct resctrl_schema
>> *schema, int closid)
>> +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int
>> closid)
>>   {
>>       struct rdt_resource *r = schema->res;
>>       struct rdt_ctrl_domain *dom;
>> diff --git a/arch/x86/kernel/cpu/resctrl/internal.h
>> b/arch/x86/kernel/cpu/resctrl/internal.h
>> index 9a3da6d49144..f2c87ca37b13 100644
>> --- a/arch/x86/kernel/cpu/resctrl/internal.h
>> +++ b/arch/x86/kernel/cpu/resctrl/internal.h
>> @@ -663,6 +663,7 @@ void __init thread_throttle_mode_init(void);
>>   void __init mbm_config_rftype_init(const char *config);
>>   void rdt_staged_configs_clear(void);
>>   void __init resctrl_sdciae_rftype_init(void);
>> +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int
>> closid);
>>   bool closid_allocated(unsigned int closid);
>>   int resctrl_find_cleanest_closid(void);
>>   diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> index 58e4df195207..51bc715bb6ae 100644
>> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
>> @@ -1922,6 +1922,25 @@ static ssize_t resctrl_sdciae_write(struct
>> kernfs_open_file *of, char *buf,
>>       return ret ?: nbytes;
>>   }
>>   +static int resctrl_sdciae_cbm_show(struct kernfs_open_file *of,
>> +                   struct seq_file *seq, void *v)
>> +{
>> +    struct resctrl_schema *s = of->kn->parent->priv;
>> +    struct rdt_resource *r = s->res;
>> +    u32 sdciae_closid;
>> +
>> +    if (!resctrl_arch_get_sdciae_enabled(RDT_RESOURCE_L3)) {
> 
> (same issue with this file appearing in all cache resources, eg. L2)

Sure. Will address it.

> 
>> +        rdt_last_cmd_puts("SDCIAE is not enabled\n");
>> +        return -EINVAL;
>> +    }
>> +
>> +    sdciae_closid = get_sdciae_closid(r);
>> +
>> +    show_doms(seq, s, sdciae_closid);
>> +
>> +    return 0;
>> +}
> 
> This really needs protection. (You should have encountered warnings
> via lockdep_assert_held(&rdtgroup_mutex) and lockdep_assert_cpus_held()
> found in the functions called.)


Sure. Will fix it.

>> +
>>   /* rdtgroup information files for one cache resource. */
>>   static struct rftype res_common_files[] = {
>>       {
>> @@ -2081,6 +2100,12 @@ static struct rftype res_common_files[] = {
>>           .seq_show    = resctrl_sdciae_show,
>>           .write        = resctrl_sdciae_write,
>>       },
>> +    {
>> +        .name        = "sdciae_cbm",
>> +        .mode        = 0444,
>> +        .kf_ops        = &rdtgroup_kf_single_ops,
>> +        .seq_show    = resctrl_sdciae_cbm_show,
>> +    },
>>       {
>>           .name        = "mode",
>>           .mode        = 0644,
>> @@ -2187,6 +2212,10 @@ void __init resctrl_sdciae_rftype_init(void)
>>       rft = rdtgroup_get_rftype_by_name("sdciae");
>>       if (rft)
>>           rft->fflags = RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE;
>> +
>> +    rft = rdtgroup_get_rftype_by_name("sdciae_cbm");
>> +    if (rft)
>> +        rft->fflags = RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE;
>>   }
>>     /**
> 
> Reinette
> 

-- 
Thanks
Babu Moger

  reply	other threads:[~2024-09-18 20:19 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-16 16:16 [PATCH 0/7] x86/resctrl : Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Babu Moger
2024-08-16 16:16 ` [PATCH 1/7] x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement Babu Moger
2024-08-17 14:50   ` Borislav Petkov
2024-08-19 20:17     ` Moger, Babu
2024-09-13 20:44   ` Reinette Chatre
2024-09-18  0:50     ` Moger, Babu
2024-08-16 16:16 ` [PATCH 2/7] x86/resctrl: Add SDCIAE feature in the command line options Babu Moger
2024-09-13 20:45   ` Reinette Chatre
2024-09-18 14:38     ` Moger, Babu
2024-08-16 16:16 ` [PATCH 3/7] x86/resctrl: Introduce sdciae_capable in rdt_resource Babu Moger
2024-09-13 20:45   ` Reinette Chatre
2024-09-18 15:27     ` Moger, Babu
2024-09-18 18:22       ` Moger, Babu
2024-09-19 15:33         ` Reinette Chatre
2024-09-20 21:05           ` Moger, Babu
2024-10-15 20:40           ` Moger, Babu
2024-10-16 15:54             ` Reinette Chatre
2024-10-16 16:46               ` Moger, Babu
2024-10-16 18:31                 ` Reinette Chatre
2024-08-16 16:16 ` [PATCH 4/7] x86/resctrl: Implement SDCIAE enable/disable Babu Moger
2024-09-13 20:46   ` Reinette Chatre
2024-09-18 16:26     ` Moger, Babu
2024-09-19 15:34       ` Reinette Chatre
2024-09-20 21:33         ` Moger, Babu
2024-08-16 16:16 ` [PATCH 5/7] x86/resctrl: Add interface to enable/disable SDCIAE Babu Moger
2024-09-13 20:51   ` Reinette Chatre
2024-09-18 20:10     ` Moger, Babu
2024-09-19 15:35       ` Reinette Chatre
2024-10-15 19:25         ` Moger, Babu
2024-10-16 15:53           ` Reinette Chatre
2024-10-16 16:52             ` Moger, Babu
2024-08-16 16:16 ` [PATCH 6/7] x86/resctrl: Introduce interface to display SDCIAE Capacity Bit Masks Babu Moger
2024-09-13 20:52   ` Reinette Chatre
2024-09-18 20:19     ` Moger, Babu [this message]
2024-08-16 16:16 ` [PATCH 7/7] x86/resctrl: Introduce interface to modify " Babu Moger
2024-09-13 20:44 ` [PATCH 0/7] x86/resctrl : Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Reinette Chatre
2024-09-17 20:51   ` Moger, Babu

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