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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d704bfc5aasm3273085ad.61.2026.08.25.19.53.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Aug 2026 19:53:59 -0700 (PDT) Message-ID: <15826e27-514c-4aaf-b56e-b40ed0bd600b@oss.qualcomm.com> Date: Wed, 26 Aug 2026 10:53:51 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: display: msm: Allow two MDSS power domains To: Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Abel Vesa , Yuanjie Yang , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260720-msm_gdsc2-v1-0-4687866d6cb0@oss.qualcomm.com> <20260720-msm_gdsc2-v1-1-4687866d6cb0@oss.qualcomm.com> <5341e732-0deb-4d00-9a7c-595e317bf1e8@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: qR-CWuOGyd-NEfpBZW7o1qyGbtCv6A9I X-Proofpoint-ORIG-GUID: qR-CWuOGyd-NEfpBZW7o1qyGbtCv6A9I X-Authority-Analysis: v=2.4 cv=I+NVgtgg c=1 sm=1 tr=0 ts=6a8e5548 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=XoI0lUbBRiva2J4xD0cA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDAyMiBTYWx0ZWRfX495cTNkFpI7s xwX0DW2IRw1ElLp/IRCLid+fBJ0D7n12E4hjHfvi2dfCrDgnQcRikotGvl5D5i4bCWyRLUHakVb 9m7Wo7YctWNUdG3XuiyXNye/rUvi2ugcEs0gLKnpnThYs4c6zhwE5t5dIijmnOd+z5MeCpJ4KsU yClC2VwJJEZvXdPKZTtwO/b4ITCYhIXNIIklCpps+nBek9rjD5mBnbB3sQea+pgpppcxVTkDLHA 5x79wkJ+mKziPCaxy8dZs5+h0A5zCqX8ZBj+sdd9atnb++3nazguN7Ek9VO3NrbUDOuLMXOKRs6 EjJtfBj0FANIYnth/NyRGQDGYbYy2tV/S6VmQNMI/UeSYV8t/SMPoMz6AVChOBOLpLyKpSVg1LS jXGsbTOjpJVDULjrbz0+v5+ycIo4tyw8yafiKvX0GiU90yKoF33AF140Vb0bBgCJwruSHM6MOz2 iNrnoukDXsJvkUkZW7A== X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDAyMiBTYWx0ZWRfX/YcuuPZwNrI9 gXVhaIPC9pB2sqwXe1TtBD9xHm7MoVkYspAunODCuzy73/T8/o+hgn6sYBHTT+jprX8lq1Y+Fyp bupMcE8LX1NiOC+JnVJj+6W3C80EOhY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-25_07,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260022 On 8/25/2026 4:30 PM, Konrad Dybcio wrote: > On 8/25/26 8:28 AM, Yongxing Mou wrote: >> >> >> On 8/17/2026 10:14 PM, Konrad Dybcio wrote: >>> On 8/17/26 4:13 PM, Konrad Dybcio wrote: >>>> On 8/13/26 9:44 AM, Yongxing Mou wrote: >>>>> >>>>> >>>>> On 7/20/2026 4:49 PM, Konrad Dybcio wrote: >>>>>> On 7/20/26 10:43 AM, Yongxing Mou wrote: >>>>>>> Kaanapali (SM8750) and Glymur use two display power domains. >>>>>>> CORE_GDSC powers the main display hardware while INT2_GDSC >>>>>>> powers a subset of SSPP blocks. >>>>>> >>>>>> Can they operate independently? Does INT2_GDSC need to be >>>>>> powered on after CORE_GDSC? >>>>>> >>>>> On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should generally track the same state, except that INT2_GDSC may be powered down when SSPP1 (VIG2/VIG3/DMA5) is unused. >>>> >>>> Is the MDSS any useful if *only* INT2_GDSC is enabled? Can the INT2_GDSC >>>> be enabled itself if CORE_GDSC is off? >>> >>> (I didn't quite know how to parse the list of states you provided in your >>> reply so I asked again) >>> >>> Konrad >> Hi, Konard. Would you recommend adding the parent clock in the clock driver, or handling 2 GDSC in the display driver? I'm preparing the next revision and would appreciate your feedback. > > Does disabling INT2 provide us with any power benefits and will the So far, I haven't found any documentation that explicitly describes a power-saving use case achieved by disabling the INT2 GDSC. The material I found instead describes it in the context of display tiering: "Goal for partial display is to tier down from premium tier to match low tier pipe configurations." > display driver do the accounting for what resources need the INT2 > GDSC specifically? Not at the moment. Our current requirement is simply to enable and disable it together with the core GDSC. > > Konrad