From: "tip-bot2 for Kim Phillips" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Kim Phillips <kim.phillips@amd.com>, Borislav Petkov <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: [tip: perf/core] perf/amd/uncore: Make L3 thread mask code more readable
Date: Tue, 17 Mar 2020 12:07:42 -0000 [thread overview]
Message-ID: <158444686229.28353.2736088400656740915.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20200313231024.17601-2-kim.phillips@amd.com>
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 9689dbbeaea884d19e3085439c6a247ef986b2af
Gitweb: https://git.kernel.org/tip/9689dbbeaea884d19e3085439c6a247ef986b2af
Author: Kim Phillips <kim.phillips@amd.com>
AuthorDate: Fri, 13 Mar 2020 18:10:23 -05:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 17 Mar 2020 13:00:49 +01:00
perf/amd/uncore: Make L3 thread mask code more readable
Convert the l3_thread_slice_mask() function to use the more readable
topology_* helper functions, more intuitive variable names like shift
and thread_mask, and BIT_ULL().
No functional changes.
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200313231024.17601-2-kim.phillips@amd.com
---
arch/x86/events/amd/uncore.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 2abcb1a..07af497 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -185,13 +185,16 @@ static void amd_uncore_del(struct perf_event *event, int flags)
*/
static u64 l3_thread_slice_mask(int cpu)
{
- int thread = 2 * (cpu_data(cpu).cpu_core_id % 4);
+ u64 thread_mask, core = topology_core_id(cpu);
+ unsigned int shift, thread = 0;
- if (smp_num_siblings > 1)
- thread += cpu_data(cpu).apicid & 1;
+ if (topology_smt_supported() && !topology_is_primary_thread(cpu))
+ thread = 1;
- return (1ULL << (AMD64_L3_THREAD_SHIFT + thread) &
- AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK;
+ shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread;
+ thread_mask = BIT_ULL(shift);
+
+ return AMD64_L3_SLICE_MASK | thread_mask;
}
static int amd_uncore_event_init(struct perf_event *event)
next prev parent reply other threads:[~2020-03-17 12:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-13 23:10 [PATCH 1/3 v2] perf/amd/uncore: Prepare L3 thread mask code for Family 19h support Kim Phillips
2020-03-13 23:10 ` [PATCH 2/3 v2] perf/amd/uncore: Make L3 thread mask code more readable Kim Phillips
2020-03-17 12:07 ` tip-bot2 for Kim Phillips [this message]
2020-03-13 23:10 ` [PATCH 3/3 v2] perf/amd/uncore: Add support for Family 19h L3 PMU Kim Phillips
2020-03-17 12:07 ` [tip: perf/core] " tip-bot2 for Kim Phillips
2020-03-17 12:07 ` [tip: perf/core] perf/amd/uncore: Prepare L3 thread mask code for Family 19h tip-bot2 for Kim Phillips
2020-03-18 2:09 ` [PATCH 1/3 v2] perf/amd/uncore: Prepare L3 thread mask code for Family 19h support Stephane Eranian
2020-03-18 14:46 ` Kim Phillips
2020-03-18 20:42 ` Peter Zijlstra
2020-03-18 21:26 ` Stephane Eranian
2020-03-23 20:50 ` Kim Phillips
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