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Fri, 24 Apr 2020 13:58:19 -0700 Received: from [172.19.2.91] (helo=xsjjollys50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jS5Ot-0007Lo-1x; Fri, 24 Apr 2020 13:58:19 -0700 From: Jolly Shah To: ard.biesheuvel@linaro.org, mingo@kernel.org, gregkh@linuxfoundation.org, matt@codeblueprint.co.uk, sudeep.holla@arm.com, hkallweit1@gmail.com, keescook@chromium.org, dmitry.torokhov@gmail.com, michal.simek@xilinx.com Cc: rajanv@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja , Jolly Shah Subject: [PATCH v5 07/25] firmware: xilinx: Remove eemi ops for clock_setdivider Date: Fri, 24 Apr 2020 13:57:49 -0700 Message-Id: <1587761887-4279-8-git-send-email-jolly.shah@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587761887-4279-1-git-send-email-jolly.shah@xilinx.com> References: <1587761887-4279-1-git-send-email-jolly.shah@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(376002)(39860400002)(136003)(346002)(396003)(46966005)(4326008)(2616005)(8676002)(5660300002)(36756003)(8936002)(9786002)(81156014)(82740400003)(186003)(7416002)(107886003)(44832011)(426003)(336012)(478600001)(316002)(26005)(6666004)(81166007)(7696005)(82310400002)(356005)(6636002)(2906002)(70586007)(47076004)(70206006)(54906003);DIR:OUT;SFP:1101; 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Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah --- drivers/clk/zynqmp/divider.c | 3 +-- drivers/clk/zynqmp/pll.c | 4 ++-- drivers/firmware/xilinx/zynqmp.c | 4 ++-- include/linux/firmware/xlnx-zynqmp.h | 6 +++++- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index e21f4ea..13041cd 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -219,7 +219,6 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, u32 div_type = divider->div_type; u32 value, div; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { @@ -233,7 +232,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) div = __ffs(div); - ret = eemi_ops->clock_setdivider(clk_id, div); + ret = zynqmp_pm_clock_setdivider(clk_id, div); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 41f376a..95fad06 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -187,7 +187,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, rate = parent_rate * m; frac = (parent_rate * f) / FRAC_DIV; - ret = eemi_ops->clock_setdivider(clk_id, m); + ret = zynqmp_pm_clock_setdivider(clk_id, m); if (ret == -EUSERS) WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name); @@ -201,7 +201,7 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); - ret = eemi_ops->clock_setdivider(clk_id, fbdiv); + ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", __func__, clk_name, ret); diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index c11b528..ef2412d 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -405,11 +405,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate); * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider); /** * zynqmp_pm_clock_getdivider() - Get the clock divider for given id @@ -740,7 +741,6 @@ static int zynqmp_pm_aes_engine(const u64 address, u32 *out) } static const struct zynqmp_eemi_ops eemi_ops = { - .clock_setdivider = zynqmp_pm_clock_setdivider, .clock_getdivider = zynqmp_pm_clock_getdivider, .clock_setrate = zynqmp_pm_clock_setrate, .clock_getrate = zynqmp_pm_clock_getrate, diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index e874f0c..023f1f9 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -296,7 +296,6 @@ struct zynqmp_pm_query_data { struct zynqmp_eemi_ops { int (*fpga_load)(const u64 address, const u32 size, const u32 flags); int (*fpga_get_status)(u32 *value); - int (*clock_setdivider)(u32 clock_id, u32 divider); int (*clock_getdivider)(u32 clock_id, u32 *divider); int (*clock_setrate)(u32 clock_id, u64 rate); int (*clock_getrate)(u32 clock_id, u64 *rate); @@ -331,6 +330,7 @@ int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); int zynqmp_pm_clock_enable(u32 clock_id); int zynqmp_pm_clock_disable(u32 clock_id); int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { @@ -361,6 +361,10 @@ static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) { return -ENODEV; } +static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ -- 2.7.4