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Sun, 31 May 2026 22:00:19 -0700 (PDT) X-Received: by 2002:a17:90b:1d51:b0:368:3830:a8bd with SMTP id 98e67ed59e1d1-36bbe0b5b21mr10537229a91.7.1780290019308; Sun, 31 May 2026 22:00:19 -0700 (PDT) Received: from [10.239.155.28] ([114.94.8.21]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c857729930esm8606486a12.16.2026.05.31.22.00.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 31 May 2026 22:00:18 -0700 (PDT) Message-ID: <158920bf-3b52-4772-9305-18afcd5807e3@oss.qualcomm.com> Date: Mon, 1 Jun 2026 13:00:12 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] dt-bindings: pinctrl: qcom,pmic-gpio: Add level-shifter function To: Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , David Collins , Subbaraman Narayanamurthy , Kamal Wadhwa , Maulik Shah , kernel@oss.qualcomm.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org References: <20260528-pinctrl-level-shifter-v2-0-3a6a025392bf@oss.qualcomm.com> <20260528-pinctrl-level-shifter-v2-2-3a6a025392bf@oss.qualcomm.com> <20260530-thankful-maroon-boar-be86f8@quoll> Content-Language: en-US From: Fenglin Wu In-Reply-To: <20260530-thankful-maroon-boar-be86f8@quoll> Content-Type: text/plain; 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Introduce a custom >> pinconf parameter "qcom,1p2v-1p8v-ls-en" for enabling or disabling the >> level-shifter function. > I don't get how PMIC, which is not a child of RPMh at all or not > talking with RPMh RSC, needs to configure its pin via RPMh. It feels it > is misrepresented. The control for enabling or disabling the bi-directional level shifter has been centralized in AOP, similar to how regulator resources are managed. This allows it to be used on a serial bus shared by multiple clients from different subsystems. Each subsystem can vote for its enable state through RPMh commands, and AOP determines the final status to turn the BIDIR_LVL_SHIFTER PMIC modules on or off. Additionally, each bi-directional level shifter shares its physical pins with a pair of PMIC GPIO modules and is mutually exclusive with other PMIC GPIO functions, which means those PMIC GPIO functions must be disabled. For these reasons, adding bi-directional level shifter software support to the pinctrl-spmi-gpio driver is considered the best approach. Let me know if you have a better suggestion. >> Additionally, add the "groups" property with the allowed group names >> that can be used to control the level-shifter function on pmh0101. >> >> Signed-off-by: Fenglin Wu >> --- >> .../bindings/pinctrl/qcom,pmic-gpio.yaml | 66 +++++++++++++++++++++- >> include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 1 + >> 2 files changed, 64 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml >> index b8109e6c2a10..19dc61ddff2d 100644 >> --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml >> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml >> @@ -119,6 +119,21 @@ properties: >> The first cell will be used to define gpio number and the >> second denotes the flags for this gpio >> >> + qcom,rpmh: >> + description: >> + Phandle to the RPMh controller device. Required for PMICs when the >> + bidirectional level shifters is used (e.g., pmh0101), to enable >> + communication with RPMh firmware for level shifter control. >> + $ref: /schemas/types.yaml#/definitions/phandle >> + >> + qcom,pmic-id: >> + description: >> + The ID of the PMIC which supports bidirectional level shifter function. >> + It is used as the RPMh resource name suffix to request control of the >> + level shifter to the RPMh firmware. >> + $ref: /schemas/types.yaml#/definitions/string >> + pattern: "^[A-N]_E[0-3]+$" > You do not get instance IDs (it's explcitly documented in docs). Okay. This is primarily for creating the resource names used to obtain the rpmh addresses from the cmd-db for the level-shifter. I can change it to a different name if you still agree to add the support in the pinctrl driver. >> + >> additionalProperties: false >> >> required: >> @@ -330,6 +345,22 @@ allOf: >> contains: >> enum: >> - qcom,pmh0101-gpio >> + then: >> + properties: >> + gpio-line-names: >> + minItems: 18 >> + maxItems: 18 >> + gpio-reserved-ranges: >> + minItems: 1 >> + maxItems: 9 >> + qcom,rpmh: true >> + qcom,pmic-id: true >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> - qcom,pmih0108-gpio >> then: >> properties: >> @@ -523,6 +554,19 @@ $defs: >> items: >> pattern: '^gpio([0-9]+)$' >> >> + groups: >> + $ref: /schemas/types.yaml#/definitions/string-array >> + description: >> + List of GPIO groups to apply properties to. Only valid for >> + function "level-shifter" on pmh0101. Valid groups are >> + gpio11, gpio12; gpio13, gpio14; gpio15, gpio16; gpio17, gpio18. >> + items: >> + enum: >> + - gpio11, gpio12 >> + - gpio13, gpio14 >> + - gpio15, gpio16 >> + - gpio17, gpio18 >> + >> function: >> items: >> - enum: >> @@ -536,6 +580,7 @@ $defs: >> - dtest4 >> - func3 # supported by LV/MV GPIO subtypes >> - func4 # supported by LV/MV GPIO subtypes >> + - level-shifter # supported only by pmh0101 >> >> bias-disable: true >> bias-pull-down: true >> @@ -592,9 +637,24 @@ $defs: >> configured as digital input. >> enum: [1, 2, 3, 4] >> >> - required: >> - - pins >> - - function >> + qcom,1p2v-1p8v-ls-en: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + description: >> + Enable or disable the bidirectional 1.2V/1.8V level shifter >> + associated with the specified GPIO group. When set to 1, an RPMh >> + vote is sent to AOP to enable the level shifter. When set to 0, >> + the vote is withdrawn. Only valid when function is "level-shifter" >> + and groups is a level-shifter GPIO pair (e.g., "gpio11, gpio12" >> + on pmh0101). > And there are no generic pinconf properties defining the voltage? The 1.2V and 1.8V voltages on each side of the bidirectional level shifter are not configurable. They are fixed in the hardware with built-in reference voltages at each side of the pins. I am adding this custom pinconf parameter mainly to control its enabling status. Also, I am adding "1p2v-1p8v" in the parameter name to provide additional clarity for users about the "level-shifter" function. > > Best regards, > Krzysztof >