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Wed, 17 Jun 2020 04:37:47 -0700 Received: from [10.140.6.6] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jlWO3-0007TR-0M; Wed, 17 Jun 2020 04:37:47 -0700 From: Srinivas Neeli To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, shubhrajyoti.datta@xilinx.com, sgoud@xilinx.com Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, git@xilinx.com Subject: [PATCH V4 6/7] gpio: zynq: Add pmc gpio support Date: Wed, 17 Jun 2020 17:07:26 +0530 Message-Id: <1592393847-1415-7-git-send-email-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592393847-1415-1-git-send-email-srinivas.neeli@xilinx.com> References: <1592393847-1415-1-git-send-email-srinivas.neeli@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(346002)(376002)(136003)(39860400002)(396003)(46966005)(26005)(107886003)(966005)(83380400001)(47076004)(4326008)(478600001)(8936002)(82740400003)(356005)(82310400002)(81166007)(316002)(336012)(7696005)(426003)(70586007)(6666004)(44832011)(70206006)(5660300002)(9786002)(186003)(6636002)(36756003)(2906002)(8676002)(2616005);DIR:OUT;SFP:1101; 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Only bank 0,1, 3 and 4 are connected to the multiplexed Input output pins. Bank 0 and 1 to mio and bank 3 and 4 to extended multiplexed input output pins. Versal devices are the industry's first adaptive compute acceleration platforms. https://www.xilinx.com/support/documentation/data_sheets/ds950-versal-overview.pdf On the Versal platform, we are using two customized GPIO controllers(IP) which were used in Zynq/ZynqMp platform. One of them present in the Platform Management Controller(PMC) block and other in Processing System(PS) block. In PMC_GPIO only Bank0,1,3 & 4 are enabled and in PS_GPIO only Bank 0 & 3 are enabled. You can find more details of GPIO IP in ZynqMP TRM General Purpose I/O(Chapter-27). https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Signed-off-by: Shubhrajyoti Datta Signed-off-by: Michal Simek --- drivers/gpio/gpio-zynq.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index b6261a3aec55..2ddb59b242e7 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c @@ -23,6 +23,7 @@ #define ZYNQ_GPIO_MAX_BANK 4 #define ZYNQMP_GPIO_MAX_BANK 6 #define VERSAL_GPIO_MAX_BANK 4 +#define PMC_GPIO_MAX_BANK 5 #define VERSAL_UNUSED_BANKS 2 #define ZYNQ_GPIO_BANK0_NGPIO 32 @@ -815,6 +816,20 @@ static const struct zynq_platform_data versal_gpio_def = { .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */ }; +static const struct zynq_platform_data pmc_gpio_def = { + .label = "pmc_gpio", + .ngpio = 116, + .max_bank = PMC_GPIO_MAX_BANK, + .bank_min[0] = 0, + .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ + .bank_min[1] = 26, + .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */ + .bank_min[3] = 52, + .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */ + .bank_min[4] = 84, + .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */ +}; + static const struct zynq_platform_data zynqmp_gpio_def = { .label = "zynqmp_gpio", .quirks = GPIO_QUIRK_DATA_RO_BUG, @@ -853,6 +868,7 @@ static const struct of_device_id zynq_gpio_of_match[] = { { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def }, + { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def }, { /* end of table */ } }; MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); -- 2.7.4