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Mon, 29 Jun 2020 17:30:16 -0700 From: Amit Sunil Dhamne To: mturquette@baylibre.com, sboyd@codeaurora.org, sboyd@kernel.org, michal.simek@xilinx.com, mark.rutland@arm.com, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, jollys@xilinx.com, tejasp@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rajan Vaja , Amit Sunil Dhamne Subject: [PATCH 3/3] clk: zynqmp: Use firmware specific mux clock flags Date: Mon, 29 Jun 2020 17:30:14 -0700 Message-Id: <1593477014-18443-4-git-send-email-amit.sunil.dhamne@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593477014-18443-1-git-send-email-amit.sunil.dhamne@xilinx.com> References: <1593477014-18443-1-git-send-email-amit.sunil.dhamne@xilinx.com> X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFTY:;SFS:(39860400002)(346002)(396003)(376002)(136003)(46966005)(107886003)(356005)(9786002)(7696005)(8936002)(26005)(47076004)(81166007)(82310400002)(82740400003)(186003)(478600001)(426003)(336012)(5660300002)(2616005)(83380400001)(4326008)(36756003)(54906003)(70586007)(316002)(8676002)(2906002)(70206006);DIR:OUT;SFP:1101; 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Signed-off-by: Rajan Vaja Signed-off-by: Amit Sunil Dhamne --- drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 +++++++++++++- drivers/clk/zynqmp/clk-zynqmp.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-m= ux-zynqmp.c index 0619414..9e365e7 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -123,7 +123,19 @@ struct clk_hw *zynqmp_clk_register_mux(const char *nam= e, u32 clk_id, init.flags =3D nodes->flag; init.parent_names =3D parents; init.num_parents =3D num_parents; - mux->flags =3D nodes->type_flag; + mux->flags =3D 0; + mux->flags |=3D (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ? + CLK_MUX_INDEX_ONE : 0; + mux->flags |=3D (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ? + CLK_MUX_INDEX_BIT : 0; + mux->flags |=3D (nodes->type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ? + CLK_MUX_HIWORD_MASK : 0; + mux->flags |=3D (nodes->type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ? + CLK_MUX_READ_ONLY : 0; + mux->flags |=3D (nodes->type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ? + CLK_MUX_ROUND_CLOSEST : 0; + mux->flags |=3D (nodes->type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ? + CLK_MUX_BIG_ENDIAN : 0; mux->hw.init =3D &init; mux->clk_id =3D clk_id; diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqm= p.h index ade5e9e..a29ab43 100644 --- a/drivers/clk/zynqmp/clk-zynqmp.h +++ b/drivers/clk/zynqmp/clk-zynqmp.h @@ -41,6 +41,14 @@ #define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) #define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) +/* Type Flags for mux clock */ +#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0) +#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1) +#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2) +#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3) +#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4) +#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5) + enum topology_type { TYPE_INVALID, TYPE_MUX, -- 2.7.4 This email and any attachments are intended for the sole use of the named r= ecipient(s) and contain(s) confidential information that may be proprietary= , privileged or copyrighted under applicable law. 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