From: qianjun <qianjun.kernel@gmail.com>
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org
Cc: linux-kernel@vger.kernel.org, qianjun <qianjun@didiglobal.com>
Subject: [PATCH] perf-c2c: Fix the wrong description.
Date: Thu, 9 Jul 2020 21:03:15 +0800 [thread overview]
Message-ID: <1594299795-39394-1-git-send-email-qianjun.kernel@gmail.com> (raw)
From: qianjun <qianjun@didiglobal.com>
Use L1Miss to replace L1Hit to describe the correct scene
Signed-off-by: qianjun <qianjun@didiglobal.com>
---
tools/perf/Documentation/perf-c2c.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt
index 98efdab..083e99a 100644
--- a/tools/perf/Documentation/perf-c2c.txt
+++ b/tools/perf/Documentation/perf-c2c.txt
@@ -186,7 +186,7 @@ For each cacheline in the 1) list we display following data:
Store Reference - Total, L1Hit, L1Miss
Total - all store accesses
L1Hit - store accesses that hit L1
- L1Hit - store accesses that missed L1
+ L1Miss - store accesses that missed L1
Load Dram
- count of local and remote DRAM accesses
--
1.8.3.1
next reply other threads:[~2020-07-09 13:07 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-09 13:03 qianjun [this message]
2020-07-22 5:03 ` jun qian
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