From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933213AbcFPBGe (ORCPT ); Wed, 15 Jun 2016 21:06:34 -0400 Received: from lucky1.263xmail.com ([211.157.147.132]:51947 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932078AbcFPBGb (ORCPT ); Wed, 15 Jun 2016 21:06:31 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 To: Doug Anderson References: <1465339484-969-1-git-send-email-dianders@chromium.org> <1465339484-969-5-git-send-email-dianders@chromium.org> <47a2dcd9-9c3c-8fde-2be0-40e305c25e8d@rock-chips.com> Cc: shawn.lin@rock-chips.com, Ulf Hansson , Kishon Vijay Abraham I , Heiko Stuebner , Rob Herring , Ziyuan Xu , Brian Norris , Adrian Hunter , "open list:ARM/Rockchip SoC..." , "linux-mmc@vger.kernel.org" , "devicetree@vger.kernel.org" , Michal Simek , soren.brinkmann@xilinx.com, "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" From: Shawn Lin Message-ID: <15960cce-354b-5eb6-79b0-19f55e840b0d@rock-chips.com> Date: Thu, 16 Jun 2016 09:06:14 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016/6/14 10:13, Doug Anderson wrote: > Shawn, > > On Mon, Jun 13, 2016 at 5:59 PM, Shawn Lin wrote: >>> Even in the case that an SoC designer didn't put a value into >>> corecfg_baseclkfreq that matched register[15:8], it seems very likely >>> that the rate returned from the clk_get_rate() would match. >>> >>> I guess what I'm saying is that, to me, it seems like my patch isn't >>> broken in any real systems. If we ever find a system that needs this >>> behavior in the future, we can add it. Until then, it seems like my >>> patch would be fine. Do you agree? >> >> >> I agree. But from the code itself, we should still use >> SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN to see if we could get >> it from internal register in case of some platforms don't >> provide the clk stuff.. Sounds sane? :) > > Could we wait until there exists a SoC that needs to provide > baseclkfreq in its sdhci_arasan_soc_ctl_map table and that needs this > value copied from register[15:8]? yes, I think the base clk got from clk framework shouldn't make any difference with that from register[15:8] if implemented. And we now decide how to get base clk in a certain variant driver which menas we know that this variant would never implement register[15:8], so it looks fine for your patch with only a nit that we should make sure we toggle up the COMMON_CLK. I saw your v2.1 to deal with it, so I think it's okay now to add Reviewed-by: Shawn Lin > > AKA: > > A) If you have a SoC where clk_get_rate() is right and software needs > to set baseclkfreq manualy, then you should include "baseclkfreq" in > your sdhci_arasan_soc_ctl_map table. This is like rk3399. Note that > if _both_ clk_get_rate() and register[15:8] are right, that's fine. > We can still use clk_get_rate() since it will be exactly the same as > register[15:8]. > > B) If you have a SoC that doesn't even expose corecfg_baseclkfreq to > software control, just don't include "baseclkfreq" in your > sdhci_arasan_soc_ctl_map table. Easy. This is how my patch treats > anyone using the current "generic" bindings, but you could easily just > specify an offset of "-1" for baseclkfreq if you didn't want to use > the generic bindings but couldn't control baseclkfreq. > > C) If you have a SoC that provides a valid value in register[15:8] and > clk_get_rate() is wrong and software is required to copy the value > from register[15:8] to baseclkfreq, technically we should fix > clk_get_rate() anyway. It's good when common clock framework provides > correct values. NOTE: It seems very unlikely to me that > register[15:8] would be right AND that software would be required to > copy this value to baseclkfreq, but I suppose there are some pretty > crazy hardware designs out there. > > D) If you have a SoC that provides a valid value in register[15:8] and > clk_get_rate() is wrong and can't be fixed (REALLY?) and software is > required to copy the value from register[15:8] to baseclkfreq, we will > need to add new code. My assertion is that such a SoC doesn't exist > and is unlikely to ever exist, so I am hesitant to add extra code to > support this SoC. > > > With my patch, A) and B) are certainly handled. I think C) is > unlikely to exist, but if it did exist then I'd say we should fix > clk_get_rate(). I think D) is VERY unlikely to exist. If I'm shown > proof of D) existing, I'm happy to submit a patch for it. Until we > see proof of D)'s existence, I don't think we should clutter the code > with support for it. > > > -Doug > > > -- Best Regards Shawn Lin