From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9B92C433DF for ; Tue, 25 Aug 2020 00:54:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD6DA2177B for ; Tue, 25 Aug 2020 00:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728310AbgHYAx6 (ORCPT ); Mon, 24 Aug 2020 20:53:58 -0400 Received: from mga07.intel.com ([134.134.136.100]:44396 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726090AbgHYAx5 (ORCPT ); Mon, 24 Aug 2020 20:53:57 -0400 IronPort-SDR: eEKKEPnG26OHp9W1S7axK2BgdVUetKgcbKa6xPud2DD1JG0MNn6s462v8n0SpSsH6VOGdJ1GmR bny+b+hDENbg== X-IronPort-AV: E=McAfee;i="6000,8403,9723"; a="220284886" X-IronPort-AV: E=Sophos;i="5.76,350,1592895600"; d="scan'208";a="220284886" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2020 17:53:57 -0700 IronPort-SDR: RkzjqVXa4XtddFfE0FLjtOwfipdWaiXtJo6k/WMnOGWBl6I0QXHA/AMuQ64IFcyspZ3kBZE5Hr K4RSBuancGOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,350,1592895600"; d="scan'208";a="281351924" Received: from unknown (HELO localhost.localdomain.bj.intel.com) ([10.238.156.127]) by fmsmga008.fm.intel.com with ESMTP; 24 Aug 2020 17:53:52 -0700 From: Cathy Zhang To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org Cc: pbonzini@redhat.com, sean.j.christopherson@intel.com, gregkh@linuxfoundation.org, tglx@linutronix.de, tony.luck@intel.com, dave.hansen@intel.com, kyung.min.park@intel.com, ricardo.neri-calderon@linux.intel.com, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, jpoimboe@redhat.com, ak@linux.intel.com, ravi.v.shankar@intel.com, Cathy Zhang Subject: [PATCH v4 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Date: Tue, 25 Aug 2020 08:47:57 +0800 Message-Id: <1598316478-23337-2-git-send-email-cathy.zhang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1598316478-23337-1-git-send-email-cathy.zhang@intel.com> References: <1598316478-23337-1-git-send-email-cathy.zhang@intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kyung Min Park Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration. A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK are available when this feature is present. The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo. This instruction is currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Kyung Min Park Signed-off-by: Cathy Zhang Reviewed-by: Tony Luck --- Changes since v3: * N/A Changes since v2: * Shorten documentation names for readability. Links to documentation can be found in the cover letter. (Dave Hansen) --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2901d5d..83fc9d3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -368,6 +368,7 @@ #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ +#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ -- 1.8.3.1