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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bd4f4bd1bc9sm545007266b.9.2026.05.18.01.05.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 May 2026 01:05:56 -0700 (PDT) Message-ID: <159aa418-ed40-479d-a635-a170e0ab06c5@oss.qualcomm.com> Date: Mon, 18 May 2026 10:05:54 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] drm/msm/a6xx: Add HFI support for CLX feature To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260516-a8xx-clx-support-v1-0-62508bf651ac@oss.qualcomm.com> <20260516-a8xx-clx-support-v1-1-62508bf651ac@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260516-a8xx-clx-support-v1-1-62508bf651ac@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: a4Sr27eowK7TPSVkFvSnH3bqb-F3vah5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE4MDA3NiBTYWx0ZWRfX2so8afCvxoDH 70/yQtunBArO+EcbHu8koYHS3Sd2d4P2PI4/jQXuDcWvz2QYQnVS/TZ0FDlMWVQcE9yG2zl52xA lU1F4DNEoSBzn24z4yvXMQxOw5RfeU2uPjZtTvGXQExzT80q0VFQ1DLuWLfCsTOob6KISGQCpmo GwyuKO7ana0UuhTOU0OGWm4LXVwCPzVH5ZOFMUTZIW5F9+7yurcwQ9jTPm6eeoz7oWZGleEG+kq NbKkLxqYV4K0diuoXfNnYhuLr+aHWGySKrkBouRSWxJgdP7NBJi3m1OYI1NFTZDs+Sjlv93aiJQ o4i+8Gch4plu60cRBtGhdAC/zoyK0pUVtNEup4I7HWmoPWTRGLy2NHj7SzNAHkyBldqYnulaeVQ Lr1e6sjfGN12nIZe7qpiz3q8OOXR4PRv3DGxULQMUR6SJq9WEx+4DtRjwj5TuRCaWuG+Pf5Dt5x QorknkzfZqgOW7sRVGg== X-Authority-Analysis: v=2.4 cv=KZ3idwYD c=1 sm=1 tr=0 ts=6a0ac867 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=2SAFw1Xh2MQk1rVR-FgA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: a4Sr27eowK7TPSVkFvSnH3bqb-F3vah5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-18_02,2026-05-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605180076 On 5/15/26 10:07 PM, Akhil P Oommen wrote: > Add support for Current Limit Extension (CLX) feature found on a few A8x > GPUs. This feature is required to limit the peak current consumption to > avoid HW spec violation on GX/MX rails. > > Add the necessary HFI interface support to pass the recommended CLX and > IFF/PCLX limits tables to the GMU. Per-GPU configuration is consumed > from the catalog entries. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 ++++++++ > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 71 +++++++++++++++++++++++++++++++++++ > 2 files changed, 86 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > index eb431e5e00b1..f6a3f1924bb3 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > @@ -34,6 +34,19 @@ struct cpu_gpu_lock { > uint64_t regs[62]; > }; > > +struct a6xx_limits_tbl { > + /** @tbl: List of limits table **/ > + struct a6xx_hfi_limits_tbl *tbl; > + /** @count: Number of entries in the list **/ > + u32 count; > +}; > + > +#define DECLARE_ADRENO_LIMITS_TABLE(name) \ > +static const struct a6xx_limits_tbl name = { \ > + .tbl = name ## _tbl, \ > + .count = ARRAY_SIZE(name ## _tbl), \ > +} > + > /** > * struct a6xx_info - a6xx specific information from device table > * > @@ -54,6 +67,8 @@ struct a6xx_info { > u32 gmu_cgc_mode; > u32 prim_fifo_threshold; > const struct a6xx_bcm *bcms; > + const struct a6xx_hfi_clx_table_v2_cmd *clx_tbl; > + const struct a6xx_limits_tbl *limits_tbl; > }; > > struct a6xx_gpu { > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > index 487c2736f2b3..13ae34d0d898 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > @@ -886,6 +886,73 @@ static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) > return 0; > } > > +static int a6xx_hfi_enable_iff_pclx(struct a6xx_gmu *gmu, const struct a6xx_limits_tbl *limits) > +{ > + struct a6xx_hfi_table_entry *entry; > + struct a6xx_hfi_table *tbl; > + size_t entry_size; > + size_t size; > + int ret; > + > + if (!limits) > + return 0; Is this considered a valid configuation (CLX on without IFF_PCLX data)? If not, let's throw an error here since it's only called from _enable_clx() Konrad