Re: Re: [PATCH] clk: eswin: Add CLK_IGNORE_UNUSED to NoC clock

["Xuyang Dong" <dongxuyang@eswincomputing.com>]

> 
> On Fri, Jun 05, 2026 at 05:21:18PM +0800, dongxuyang@eswincomputing.com wrote:
> > From: Xuyang Dong <dongxuyang@eswincomputing.com>
> > 
> > The gate_noc_nsp_clk provides the essential clock source for NPU,
> > DSP, and PCIe subsystems. During kernel init, the clock framework
> > attempts to disable unused clocks when clk_ignore_unused kernel
> > parameter is not set.
> > However, gate_noc_nsp_clk is required to remain enabled for these
> > critical subsystems to function properly, causing PCIe boot failures
> > when auto-disabled.
> > 
> > Add CLK_IGNORE_UNUSED flag to gate_noc_nsp_clk to ensure it stays
> > enabled even when clk_ignore_unused is not specified in kernel
> > command line.
> > 
> > Fixes: cd44f127c1d4 ("clk: eswin: Add eic7700 clock driver")
> > Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
> 
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> 
> FYI, I posted a series to implement sync_state support for the clk
> subsystem, which should fix these type of issues for the long term. If
> you happen to have time, I would appreciate it if you have time to test
> this series on your hardware, and drop a Tested-by.
> 
> https://lore.kernel.org/linux-clk/20260603-clk-sync-state-v1-0-457120eed200@redhat.com/
> 
> I have a new series ready that I'm planning to post tomorrow. I'm
> waiting to hear back about the ongoing conversation on that thread.
> 
> Once this lands, there shouldn't be much need for the CLK_IGNORE_UNUSED
> flag. I'm curious if you revert this patch in your tree if the need for the
> flag goes away with the sync_state changes applied.
> 
> Let's get your change in the tree though. If we merged sync_state today,
> it won't be eligible to be backported to the stable kernels, and the
> CLK_IGNORE_UNUSED flag is an easier backport.
> 

Hi Brian,

Thank you for your patch set above. However, we still need this fix patch 
at the moment, because gate_noc_nsp_clk still needs to be enabled when 
accessing PCIe.

Best regards,
Xuyang Dong