From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E05ECC433EF for ; Tue, 21 Jun 2022 01:40:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244066AbiFUBki (ORCPT ); Mon, 20 Jun 2022 21:40:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231894AbiFUBkh (ORCPT ); Mon, 20 Jun 2022 21:40:37 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA6B51EAEE; Mon, 20 Jun 2022 18:40:29 -0700 (PDT) X-UUID: f77b707e3cad4dbc9feeddcebce34a58-20220621 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:ef5d236d-a84e-4649-b368-910fbdaa791d,OB:10,L OB:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:50 X-CID-INFO: VERSION:1.1.6,REQID:ef5d236d-a84e-4649-b368-910fbdaa791d,OB:10,LOB :0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:50 X-CID-META: VersionHash:b14ad71,CLOUDID:93d70cea-f7af-4e69-92ee-0fd74a0c286c,C OID:325a170b1804,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: f77b707e3cad4dbc9feeddcebce34a58-20220621 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 870076133; Tue, 21 Jun 2022 09:40:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 21 Jun 2022 09:40:24 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 21 Jun 2022 09:40:24 +0800 Message-ID: <15cb231934de2f69db1c64cb2aa8bc8704b7201b.camel@mediatek.com> Subject: Re: [PATCH v12 02/14] drm/mediatek: dpi: Add support for quantization range From: CK Hu To: Bo-Chen Chen , , , , , , , CC: , , , , , , , , , , Date: Tue, 21 Jun 2022 09:40:24 +0800 In-Reply-To: <20220620121028.29234-3-rex-bc.chen@mediatek.com> References: <20220620121028.29234-1-rex-bc.chen@mediatek.com> <20220620121028.29234-3-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bo-Chen: On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote: > For RGB colorimetry, CTA-861 support both limited and full range data > when receiving video with RGB color space. > We use drm_default_rgb_quant_range() to determine the correct > setting. Reviewed-by: CK Hu > > Signed-off-by: Bo-Chen Chen > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++-------- > ---- > 1 file changed, 21 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index e61cd67b978f..21ad5623b568 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -235,16 +235,30 @@ static void mtk_dpi_config_fb_size(struct > mtk_dpi *dpi, u32 width, u32 height) > mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); > } > > -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, > - struct mtk_dpi_yc_limit > *limit) > +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) > { > - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, > + struct mtk_dpi_yc_limit limit; > + > + if (drm_default_rgb_quant_range(&dpi->mode) == > + HDMI_QUANTIZATION_RANGE_LIMITED) { > + limit.y_bottom = 0x10; > + limit.y_top = 0xfe0; > + limit.c_bottom = 0x10; > + limit.c_top = 0xfe0; > + } else { > + limit.y_bottom = 0; > + limit.y_top = 0xfff; > + limit.c_bottom = 0; > + limit.c_top = 0xfff; > + } > + > + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, > Y_LIMINT_BOT_MASK); > - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, > + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, > Y_LIMINT_TOP_MASK); > - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, > + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, > C_LIMIT_BOT_MASK); > - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, > + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, > C_LIMIT_TOP_MASK); > } > > @@ -449,7 +463,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) > static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > struct drm_display_mode *mode) > { > - struct mtk_dpi_yc_limit limit; > struct mtk_dpi_polarities dpi_pol; > struct mtk_dpi_sync_param hsync; > struct mtk_dpi_sync_param vsync_lodd = { 0 }; > @@ -484,11 +497,6 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", > pll_rate, vm.pixelclock); > > - limit.c_bottom = 0x0010; > - limit.c_top = 0x0FE0; > - limit.y_bottom = 0x0010; > - limit.y_top = 0x0FE0; > - > dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; > dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; > dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? > @@ -536,7 +544,7 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > else > mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); > > - mtk_dpi_config_channel_limit(dpi, &limit); > + mtk_dpi_config_channel_limit(dpi); > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > mtk_dpi_config_yc_map(dpi, dpi->yc_map);