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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9832f8c16csm614132566b.16.2026.03.24.02.21.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2026 02:21:44 -0700 (PDT) Message-ID: <15d0ea68-8ee0-4937-87a0-7ccd8969036e@oss.qualcomm.com> Date: Tue, 24 Mar 2026 10:21:42 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock To: Dmitry Baryshkov , Abel Vesa Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Nitin Rawat References: <20260323-eliza-gcc-set-ufs-axi-phyforce-mem-core-on-v1-1-b6b7a6f3f8c5@oss.qualcomm.com> <26twtzbvqcevl7jq6idkhhhasf4kuu6a6p6qby2plcg4a3vola@exafx7os7jls> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <26twtzbvqcevl7jq6idkhhhasf4kuu6a6p6qby2plcg4a3vola@exafx7os7jls> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI0MDA3NCBTYWx0ZWRfX8KnXBY1AIKAr QTJlgQvWX57w6o8AsA14ImQKRLeCfeMZt/dO+XC0LxT+nzZZUMv7UD9YWnGswCz0YrtxXZ5QmlA 9A4sVwXHc2yhnurT7G/FxNwTgUNPkaJwUgTNsLw5wcP8Mcgt+DkLss8tsnhVEn/stwWpIDHxCg3 eIlAl5w9WmKnJ+q4erAI8yMuEetl2uMfkRPlapAouSGkD9Iyvw4wSSMVwiVYxRfcCc2zAr3RJbC nlAVAcoHCVeUT0QZKyfFtv27nYzcgAmvQ4eOT3yOWhAxEFrhtCd6pnvR1aNoZ9QMg3XcgqX7Uoy ECw42GsjIYMkrV007EP9XujuScSwYMxnloN/4neiPSDC6bXFiAQDK9TPmK0D1yMWmXNSQIUdxsh QF7EMh2+vT1thMQuQ5/C6LYA1OYKF1u5WxpwZVrZDj/JrUMYhqRFsR2f1yM/a823SrswNHMAQ1C J7yMwQU1MRCrvLTcXZg== X-Proofpoint-ORIG-GUID: tiHyoDiEzP8xQePCYBVq6WweqOcwEEBS X-Authority-Analysis: v=2.4 cv=F6hat6hN c=1 sm=1 tr=0 ts=69c257aa cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=553ZhuPF3g2HGwrCK6AA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: tiHyoDiEzP8xQePCYBVq6WweqOcwEEBS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-24_02,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603240074 On 3/23/26 8:25 PM, Dmitry Baryshkov wrote: > On Mon, Mar 23, 2026 at 08:57:12PM +0200, Abel Vesa wrote: >> According to internal documentation, the UFS AXI PHY clock requires >> FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this, >> the UFS controller fails when operating in MCQ mode, which is already >> enabled in the device tree. >> >> The UFS PHY ICE core clock already has this bit set, so apply the same >> configuration to the UFS PHY AXI clock. >> >> Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza") >> Reported-by: Nitin Rawat >> Signed-off-by: Abel Vesa >> --- >> drivers/clk/qcom/gcc-eliza.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) > > Reviewed-by: Dmitry Baryshkov > > Do we need to apply the same fix to any other platform? FWIW on msm-5.10 (8450 kernel, from before-MCQ times) there's this excerpt in ufs-qcom.c: static void ufs_qcom_force_mem_config(struct ufs_hba *hba) { struct ufs_clk_info *clki; /* * Configure the behavior of ufs clocks core and peripheral * memory state when they are turned off. * This configuration is required to allow retaining * ICE crypto configuration (including keys) when * core_clk_ice is turned off, and powering down * non-ICE RAMs of host controller. * * This is applicable only to gcc clocks. */ list_for_each_entry(clki, &hba->clk_list_head, list) { /* skip it for non-gcc (rpmh) clocks */ if (!strcmp(clki->name, "ref_clk")) continue; if (!strcmp(clki->name, "core_clk_ice") || !strcmp(clki->name, "core_clk_ice_hw_ctl")) qcom_clk_set_flags(clki->clk, CLKFLAG_RETAIN_MEM); else qcom_clk_set_flags(clki->clk, CLKFLAG_NORETAIN_MEM); qcom_clk_set_flags(clki->clk, CLKFLAG_NORETAIN_PERIPH); qcom_clk_set_flags(clki->clk, CLKFLAG_PERIPH_OFF_CLEAR); } } i.e.: * force_mem_core(true) for ICE, force_mem_core(false) otherwise * set_force_periph_on(false) for all * set_force_periph_off(false) for all Notably, the Adreno driver messes with some of these settings too, as does the DWC3 one. Older kernels (msm-4.19) also do so in MDSS, GDSC, CVP, camera MMC, PCIe drivers Konrad