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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF0002BA4C.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.113.7 via Frontend Transport; Tue, 9 Jun 2026 04:47:18 +0000 Received: from satlexmb10.amd.com (10.181.42.219) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 8 Jun 2026 23:47:18 -0500 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb10.amd.com (10.181.42.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 8 Jun 2026 23:47:18 -0500 Received: from [10.136.43.95] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Mon, 8 Jun 2026 23:47:16 -0500 Message-ID: <160328b1-bc66-4748-bf5c-870bac6a2d10@amd.com> Date: Tue, 9 Jun 2026 10:17:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/3] cpufreq/amd-pstate: Toggle auto_sel in active mode on shared memory systems To: Marco Scardovi CC: , , , , , , , References: <20260608073614.5738-1-scardracs@disroot.org> <20260608073614.5738-3-scardracs@disroot.org> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <20260608073614.5738-3-scardracs@disroot.org> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: chiz3eCJzc1SSc04JPET0peGVk8q3B3yDts5wxfgXrzrD1GisW7AbCuZ7FHRel/ZmC6EIhCP1cCfF1/ojiczzM58DXzKqcMkENzkMX7dB+WcTkdmxMuA80opVR+Uk//iKQ1i2gg5IQILw71ERCZ2sZfQLgCu1mzEhzOTjk8LABsmqO+QRIZh13NcF0X6ONNJF5YZNTImFuqvxCPIFwc06qkE+2aSVjNY+VtEi7vJBXE5papnPfODK/RR3djtIpbbTXKDO/7h6ndxiHMUaFtHzinBZrAIt4mxYVqdTWyto48z0biG0R3EMkoZO8EixCatM2tsupCayhtX3ttYTn90Lw9BqpiInisgY5AnHRebazCD0TI/dX7/ybbSACM7UgFc52bSoRDsY6c5j587kRxYYiHnu673VNGgUgySVGPNXzgXEy+Tq25T5xhm8rBV1HAh X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2026 04:47:18.9718 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e372047-5a34-4137-c483-08dec5e22fe9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9342 Hello Marco, On 6/8/2026 1:01 PM, Marco Scardovi wrote: > On shared memory systems, the EPP configuration path (handled via > cppc_set_epp_perf()) is responsible for toggling on the CPPC autonomous > selection register (auto_sel). > > Currently, shmem_init_perf() returns early without doing any of the auto_sel > configuration steps if cppc_state is AMD_PSTATE_ACTIVE. This skips enabling > auto_sel, leaving the CPU in non-autonomous mode. > > Remove the early return check in shmem_init_perf() when cppc_state is > AMD_PSTATE_ACTIVE. Toggling auto_sel is necessary for the active mode on > shared memory systems to function based on the ACPI spec for CPPC v2 and > below. > > Fixes: 2dd6d0ebf740 ("cpufreq: amd-pstate: Add guided autonomous mode") > Assisted-by: Antigravity:gemini-3.5-flash > Signed-off-by: Marco Scardovi Feel free to include: Reviewed-by: K Prateek Nayak -- Thanks and Regards, Prateek