From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E111FC55178 for ; Thu, 29 Oct 2020 10:51:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 82A2120754 for ; Thu, 29 Oct 2020 10:51:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rwQmXGUA"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TpQj9EBT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726873AbgJ2Kvo (ORCPT ); Thu, 29 Oct 2020 06:51:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725927AbgJ2Kvl (ORCPT ); Thu, 29 Oct 2020 06:51:41 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51E9EC0613CF; Thu, 29 Oct 2020 03:51:41 -0700 (PDT) Date: Thu, 29 Oct 2020 10:51:39 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1603968699; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hUo9vUxJALWoRbeGWl9eG8dvMrTMEjVqiCq4f6+uwQA=; b=rwQmXGUAlBbJkzM/CLWhi5WGFjF67Y1Fb+/3JaItZ0oQnEG2fCgJWr8mBfLaxjRnQiB7xo FSO+mwWIrdHW8pVAceC3nZnpwxuGY/UpuOjbAkSBQmTlGKEwXKJsgTUgdQpC0J5ys9N4w2 tE2/szlpHvTQ1v9DuDgCrqZ/7Znecb3lcbVXE1uo+U1X1hjcvl1nQM+PFXCbBxFGcR3B54 8V5+JbzzlmL8RLK88thSpCpGOl61teV4G99QkB+pPdr0vlfosvSn9hyx5qBt+QATp9tRGw /Gge9Pa9vVaNgkhQgCo60KaBZt3IsbL14AzbMDyQIXfDK9XnsbCTSjVjgYyRJw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1603968699; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hUo9vUxJALWoRbeGWl9eG8dvMrTMEjVqiCq4f6+uwQA=; b=TpQj9EBT1uKqz03IBQFZKYfB39COGdEBjzympdQbBS8uMeg98VG7UeWR6vnmiAfKi9zadX J+9v28KLBDAIcVCw== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/msr: Add Rocket Lake CPU support Cc: Kan Liang , "Peter Zijlstra (Intel)" , x86 , LKML In-Reply-To: <20201019153528.13850-3-kan.liang@linux.intel.com> References: <20201019153528.13850-3-kan.liang@linux.intel.com> MIME-Version: 1.0 Message-ID: <160396869901.397.12647985959685130395.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 907a196fbc70a48338ee8512da32f70fd33c97eb Gitweb: https://git.kernel.org/tip/907a196fbc70a48338ee8512da32f70fd33c97eb Author: Kan Liang AuthorDate: Mon, 19 Oct 2020 08:35:27 -07:00 Committer: Peter Zijlstra CommitterDate: Thu, 29 Oct 2020 11:00:40 +01:00 perf/x86/msr: Add Rocket Lake CPU support Like Ice Lake and Tiger Lake, PPERF and SMI_COUNT MSRs are also supported by Rocket Lake. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20201019153528.13850-3-kan.liang@linux.intel.com --- arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 4be8f9c..680404c 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -99,6 +99,7 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ICELAKE_D: case INTEL_FAM6_TIGERLAKE_L: case INTEL_FAM6_TIGERLAKE: + case INTEL_FAM6_ROCKETLAKE: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break;