From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CD56C388F9 for ; Wed, 11 Nov 2020 13:36:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 162A1206D9 for ; Wed, 11 Nov 2020 13:36:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DGMXv9vt"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SGUIHbaT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727074AbgKKNgi (ORCPT ); Wed, 11 Nov 2020 08:36:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727029AbgKKNg1 (ORCPT ); Wed, 11 Nov 2020 08:36:27 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45275C0613D4; Wed, 11 Nov 2020 05:36:27 -0800 (PST) Date: Wed, 11 Nov 2020 13:36:24 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1605101785; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7XC9D+el1FoWHK6clw661OrmDucdSAs01LvaDazMEkM=; b=DGMXv9vtd6zj0Wu2nbzOV/Rk/s51rS1zFYCfz4PE1AWexr2iFs0JYjp1LsVJoRp246utqL /sHapNsafjrk5X7leA445YQb4r3gFK4vVPMHBzuibks6wpu/2Lq1P2s1KSwnvvISF4xG8I g2Tv9LTJAgz/t40DAeEfONuPYIVcHz4s8a1ugEalrNGY572GbfiYoWV7SqunjQXkKh1Agg MOkfJxwZaDx+DY3He4kK2dCNFg/UGoNPSXbFh4SC45zT1iVP6Zr5+VTJpHszR/aVNGO2rG hJi0Z31b/82acmCCWzSFaCIa87u4e/0+gTlJZLsR/a1AoV0E6dgXFhlNWmY6FQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1605101785; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7XC9D+el1FoWHK6clw661OrmDucdSAs01LvaDazMEkM=; b=SGUIHbaT9Z3EFQsraiyGvvaXJsaoubBP2/K3MhDuznkRSl3A8zp3eToB8owS7+BgTlOtTO V/NIE4HUnNL2k1BA== From: "tip-bot2 for Thomas Gleixner" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/fpu] x86/fpu: Simplify fpregs_[un]lock() Cc: Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20201027101349.455380473@linutronix.de> References: <20201027101349.455380473@linutronix.de> MIME-Version: 1.0 Message-ID: <160510178403.11244.2199301004015376864.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/fpu branch of tip: Commit-ID: 5f0c71278d6848b4809f83af90f28196e1505ab1 Gitweb: https://git.kernel.org/tip/5f0c71278d6848b4809f83af90f28196e1505ab1 Author: Thomas Gleixner AuthorDate: Tue, 27 Oct 2020 11:09:50 +01:00 Committer: Thomas Gleixner CommitterDate: Wed, 11 Nov 2020 14:35:16 +01:00 x86/fpu: Simplify fpregs_[un]lock() There is no point in disabling preemption and then disabling bottom halfs. Just disabling bottom halfs is sufficient as it implicitly disables preemption on !RT kernels. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20201027101349.455380473@linutronix.de --- arch/x86/include/asm/fpu/api.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h index dcd9503..2c5bef7 100644 --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -29,17 +29,18 @@ extern void fpregs_mark_activate(void); * A context switch will (and softirq might) save CPU's FPU registers to * fpu->state and set TIF_NEED_FPU_LOAD leaving CPU's FPU registers in * a random state. + * + * local_bh_disable() protects against both preemption and soft interrupts + * on !RT kernels. */ static inline void fpregs_lock(void) { - preempt_disable(); local_bh_disable(); } static inline void fpregs_unlock(void) { local_bh_enable(); - preempt_enable(); } #ifdef CONFIG_X86_DEBUG_FPU