From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B2CEC64E75 for ; Thu, 26 Nov 2020 12:42:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1DE9720B80 for ; Thu, 26 Nov 2020 12:42:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389460AbgKZMlt (ORCPT ); Thu, 26 Nov 2020 07:41:49 -0500 Received: from inva020.nxp.com ([92.121.34.13]:43166 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389265AbgKZMls (ORCPT ); Thu, 26 Nov 2020 07:41:48 -0500 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 61FA71A0685; Thu, 26 Nov 2020 13:41:46 +0100 (CET) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 54B621A00EF; Thu, 26 Nov 2020 13:41:46 +0100 (CET) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id D408E2026B; Thu, 26 Nov 2020 13:41:45 +0100 (CET) From: Abel Vesa To: Stephen Boyd , Sascha Hauer , Peng Fan , Fabio Estevam , Anson Huang , Dong Aisheng , Jacky Bai Cc: NXP Linux Team , linux-clk@vger.kernel.org, Linux Kernel Mailing List , linux-arm-kernel@lists.infradead.org, Abel Vesa Subject: [PATCH v2 4/5] clk: imx: composite-8m: Add DRAM clock registration variant Date: Thu, 26 Nov 2020 14:40:08 +0200 Message-Id: <1606394409-12755-5-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606394409-12755-1-git-send-email-abel.vesa@nxp.com> References: <1606394409-12755-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The switch between parents for dram_apb and dram_alt is done in EL3, so make all the ops read-only. That means none of the ops that write any of the registers is used for such a clock. Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-composite-8m.c | 12 +++++++++++- drivers/clk/imx/clk.h | 7 +++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 2c309e3..cf0c2b4 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -184,6 +184,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, struct clk_mux *mux = NULL; const struct clk_ops *divider_ops; const struct clk_ops *mux_ops; + const struct clk_ops *gate_ops; mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) @@ -206,16 +207,25 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, div->width = PCG_CORE_DIV_WIDTH; divider_ops = &clk_divider_ops; mux_ops = &imx8m_clk_composite_mux_ops; + gate_ops = &clk_gate_ops; } else if (composite_flags & IMX_COMPOSITE_BUS) { div->shift = PCG_PREDIV_SHIFT; div->width = PCG_PREDIV_WIDTH; divider_ops = &imx8m_clk_composite_divider_ops; mux_ops = &imx8m_clk_composite_mux_ops; + gate_ops = &clk_gate_ops; + } else if (composite_flags & IMX_COMPOSITE_RO) { + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + divider_ops = &clk_divider_ro_ops; + mux_ops = &clk_mux_ro_ops; + gate_ops = &clk_gate_ro_ops; } else { div->shift = PCG_PREDIV_SHIFT; div->width = PCG_PREDIV_WIDTH; divider_ops = &imx8m_clk_composite_divider_ops; mux_ops = &clk_mux_ops; + gate_ops = &clk_gate_ops; flags |= CLK_SET_PARENT_GATE; } @@ -233,7 +243,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, mux_ops, div_hw, - divider_ops, gate_hw, &clk_gate_ops, flags); + divider_ops, gate_hw, gate_ops, flags); if (IS_ERR(hw)) goto fail; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 4f04c82..878ceb0 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -532,6 +532,7 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, #define IMX_COMPOSITE_CORE BIT(0) #define IMX_COMPOSITE_BUS BIT(1) +#define IMX_COMPOSITE_RO BIT(2) struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, @@ -557,6 +558,12 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, IMX_COMPOSITE_CORE, \ CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) +#define imx8m_clk_hw_composite_dram(name, parent_names, reg) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_RO, \ + CLK_GET_RATE_NOCACHE | CLK_GET_PARENT_NOCACHE \ + | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \ flags) \ to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \ -- 2.7.4