From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A13D9C71156 for ; Thu, 3 Dec 2020 09:08:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5022C22256 for ; Thu, 3 Dec 2020 09:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388519AbgLCJIS (ORCPT ); Thu, 3 Dec 2020 04:08:18 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:39388 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387757AbgLCJIN (ORCPT ); Thu, 3 Dec 2020 04:08:13 -0500 Date: Thu, 03 Dec 2020 09:07:30 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1606986451; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RgeQfumqpHMIZDAZQAL3F9T92x5EwmAFc2PXfbA/u3I=; b=Z2e4y0UtnksgMiZctvONoMm+kMyWL0hT8AQT2+bAtPUCrSu73VxhchTzobUrElELf8RkWV UTU38qeVEoCm4oFN2M+zZ4RObSJQjrXVDevlc1DgTwddlN8vyGVxTyZHU1rSWA/qHnOfmK Tmq4YLAQGkOcjQaUweK+MbTc2k6jsVI0j4mBNb09F3ORYQCSXzsGPNeVt41DR7Iya4q23H 1Bcala2jgQrMDKIixyzqEMX2g+GZrr4iB9i29AI6ReWUibnhu5q9yO28h7ghD6FGQTVoIR lWkhVPF0nHLby6B+Ztc84MG9jfXTkpw9KAylhEnAtFoiX36wco+T4yxg0OWe2Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1606986451; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RgeQfumqpHMIZDAZQAL3F9T92x5EwmAFc2PXfbA/u3I=; b=2/xuGemmJ2C8GT4cyk+nQxYf2f68pfVB3m7osOx3YtDKjjiThhXmbMid4M7CEQEifl7J85 HEo7s+EJedH8ABDA== From: "tip-bot2 for Peter Zijlstra" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] arm64/mm: Implement pXX_leaf_size() support Cc: "Peter Zijlstra (Intel)" , Will Deacon , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20201126125747.GG2414@hirez.programming.kicks-ass.net> References: <20201126125747.GG2414@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Message-ID: <160698645060.3364.4631972091195475660.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 311c656945eccc9304aa4e8f3dee7cbfdbabb72d Gitweb: https://git.kernel.org/tip/311c656945eccc9304aa4e8f3dee7cbfdbabb72d Author: Peter Zijlstra AuthorDate: Fri, 13 Nov 2020 11:46:06 +01:00 Committer: Peter Zijlstra CommitterDate: Thu, 03 Dec 2020 10:00:31 +01:00 arm64/mm: Implement pXX_leaf_size() support ARM64 has non-pagetable aligned large page support with PTE_CONT, when this bit is set the page is part of a super-page. Match the hugetlb code and support these super pages for PTE and PMD levels. This enables PERF_SAMPLE_{DATA,CODE}_PAGE_SIZE to report accurate pagetable leaf sizes. Signed-off-by: Peter Zijlstra (Intel) Acked-by: Will Deacon Link: https://lkml.kernel.org/r/20201126125747.GG2414@hirez.programming.kicks-ass.net --- arch/arm64/include/asm/pgtable.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 5628289..dc6e2d9 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -415,6 +415,7 @@ static inline int pmd_trans_huge(pmd_t pmd) #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) #define pmd_young(pmd) pte_young(pmd_pte(pmd)) #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) +#define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) @@ -511,6 +512,9 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, PMD_TYPE_SECT) #define pmd_leaf(pmd) pmd_sect(pmd) +#define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) +#define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) + #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 static inline bool pud_sect(pud_t pud) { return false; } static inline bool pud_table(pud_t pud) { return true; }