From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.mindbit.ro (xs1.mindbit.ro [80.86.107.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94C903CF686 for ; Thu, 2 Apr 2026 17:11:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.86.107.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775149904; cv=none; b=AhjUD0HuzEunQN64FDl+e4pC7poBeWlfGmzWfMWJBKm6VvJCyeWrIZuzsIWOVKRbmK01IDli6mx9+nuCd0PrrZPGnhetCKhIysA1Rc5kFr/RfvSaR2h1wnoQjh9GulpKq1YeA9cEECYjWbV1LNXQr80pOIVeBEw6FbCykO0kndY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775149904; c=relaxed/simple; bh=TUv3E9PYzxGbmdwUAOmRjv+WWjpgyoFpzMfQSOQqP5w=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=aq4Kc67x9ad3QsADsIf5EsGd1Tjgo7onEoBWSIQclIw7IjKv2rBhRlEbKcj3BnWeOmvv59rGUAPRufjU2r9sPB2K8YXJZZsqOyws2nALvZpRz6tO385U6/0hAgQ4FReoYYRl5pRGq4eR8SBaWBodOpHe97HUfgXe2hFKvoqfjh4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net; spf=pass smtp.mailfrom=rendec.net; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b=rtevF0Bq; arc=none smtp.client-ip=80.86.107.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rendec.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b="rtevF0Bq" Received: from dog.kanata.rendec.net (pool-174-112-193-187.cpe.net.cable.rogers.com [174.112.193.187]) by mail.mindbit.ro (Postfix) with ESMTPSA id EF6D9C2526; Thu, 2 Apr 2026 20:11:37 +0300 (EEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.mindbit.ro EF6D9C2526 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rendec.net; s=default; t=1775149899; bh=VP3eKSeKvBKbP4cQbBd8Kle/N4kcxfSYc0NyqfVXhio=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=rtevF0BqNQDNJU6nVSkOjeEM4Wvny+2+TPoVOA/hZWVCaurRAbVyWu+AnUsXCWfPR gSxBvtnM5uuIpPcwdmNQ/AEUDE7EacSVwXvBZNABYv3juE4z3v4e4nPFQyRLFi6omZ 5rd+4IDYDNBtlXHJ/iw47UXFIHCmrdioBI0huRxpG1TDr9pXEs0CFix07MGgcu/mVg KXCDM8blk3yR2moIWKrxTFaig+PQg5MIg6zPY5wCOH0FzGuc8YIfVx9ZZGhfyWYp/g aNrp0STi+8lYR7kQci9w1bujc5Y45zNdiV1ceTutkpIEo0pRyQ+LOrqHNDKQ03eFmw GcPjb+DUtktGg== Message-ID: <160cd0288aabf32fc17e4fde518cb9e7921ad2aa.camel@rendec.net> Subject: Re: [patch V5 07/15] scripts/gdb: Update x86 interrupts to the array based storage From: Radu Rendec To: Thomas Gleixner , LKML Cc: x86@kernel.org, Michael Kelley , Dmitry Ilvokhin , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier Date: Thu, 02 Apr 2026 13:11:36 -0400 In-Reply-To: <20260401201348.491212585@kernel.org> References: <20260401195625.213446764@kernel.org> <20260401201348.491212585@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2026-04-01 at 23:52 +0200, Thomas Gleixner wrote: > From: Thomas Gleixner >=20 > x86 changed the interrupt statistics from a struct with individual member= s > to an counter array. It also provides a corresponding info array with the > strings for prefix and description and an indicator to skip the entry. >=20 > Update the already out of sync GDB script to use the counter and the info > array, which keeps the GDB script in sync automatically. >=20 > Signed-off-by: Thomas Gleixner > Tested-by: Florian Fainelli > Reviewed-by: Florian Fainelli > --- > V5: Bring the show_err_irq() back as it is used on mips > =C2=A0=C2=A0=C2=A0 Fix the index calculation for the show bitmap so it wo= rks with more than one > =C2=A0=C2=A0=C2=A0 unsigned long. > V4: Adopted to irq_stat_count_show bitmap and removed the duplicate ERR/M= IS output > V3: New patch - Radu > --- > =C2=A0scripts/gdb/linux/interrupts.py |=C2=A0=C2=A0 81 +++++++++++-------= ---------------------- > =C2=A01 file changed, 23 insertions(+), 58 deletions(-) > --- a/scripts/gdb/linux/interrupts.py > +++ b/scripts/gdb/linux/interrupts.py > @@ -90,71 +90,29 @@ irq_desc_type =3D utils.CachedType("struct > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0 return text > =C2=A0 > -def show_irq_err_count(prec): > -=C2=A0=C2=A0=C2=A0 cnt =3D utils.gdb_eval_or_none("irq_err_count") > -=C2=A0=C2=A0=C2=A0 text =3D "" > -=C2=A0=C2=A0=C2=A0 if cnt is not None: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D "%*s: %10u\n" % (pr= ec, "ERR", cnt['counter']) > -=C2=A0=C2=A0=C2=A0 return text > - Nit: show_irq_err_count() is unchanged, and I see no obvious reason to move it down below. Keeping it here would exclude it from the patch altogether, making the patch shorter and easier to read/review. > -def x86_show_irqstat(prec, pfx, field, desc): > -=C2=A0=C2=A0=C2=A0 irq_stat =3D gdb.parse_and_eval("&irq_stat") > +def x86_show_irqstat(prec, pfx, idx, desc): > +=C2=A0=C2=A0=C2=A0 irq_stat =3D gdb.parse_and_eval("&irq_stat.counts[%d]= " %idx) > =C2=A0=C2=A0=C2=A0=C2=A0 text =3D "%*s: " % (prec, pfx) > =C2=A0=C2=A0=C2=A0=C2=A0 for cpu in cpus.each_online_cpu(): > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 stat =3D cpus.per_cpu(ir= q_stat, cpu) > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D "%10u " % (stat[fie= ld]) > -=C2=A0=C2=A0=C2=A0 text +=3D "=C2=A0 %s\n" % (desc) > -=C2=A0=C2=A0=C2=A0 return text > - > -def x86_show_mce(prec, var, pfx, desc): > -=C2=A0=C2=A0=C2=A0 pvar =3D gdb.parse_and_eval(var) > -=C2=A0=C2=A0=C2=A0 text =3D "%*s: " % (prec, pfx) > -=C2=A0=C2=A0=C2=A0 for cpu in cpus.each_online_cpu(): > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D "%10u " % (cpus.per= _cpu(pvar, cpu).dereference()) > -=C2=A0=C2=A0=C2=A0 text +=3D "=C2=A0 %s\n" % (desc) > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D "%10u " % (stat.der= eference()) Something is wrong here. The counters for the arch specific interrupts are not aligned with the generic ones. Sample from my VM setup: (gdb) lx-interruptlist=20 CPU0 CPU1 CPU2 CPU3 =20 1: 0 0 9 0 IO-APIC 1-edge i804= 2 4: 0 0 0 267 IO-APIC 4-edge ttyS= 0 9: 0 0 0 0 IO-APIC 9-fasteoi acpi 12: 0 15 0 0 IO-APIC 12-edge i804= 2 [...] NMI: 0 0 0 0 Non-maskable interrupts LOC: 3925 3997 4281 3972 Local timer interrupts PMI: 0 0 0 0 Performance monitoring i= nterrupts [...] If I remove the space in "%10u " it becomes aligned but then the description is no longer aligned. > +=C2=A0=C2=A0=C2=A0 text +=3D desc > =C2=A0=C2=A0=C2=A0=C2=A0 return text > =C2=A0 > =C2=A0def x86_show_interupts(prec): > -=C2=A0=C2=A0=C2=A0 text =3D x86_show_irqstat(prec, "NMI", '__nmi_count',= 'Non-maskable interrupts') > +=C2=A0=C2=A0=C2=A0 info_type =3D gdb.lookup_type('struct irq_stat_info') > +=C2=A0=C2=A0=C2=A0 info =3D gdb.parse_and_eval('irq_stat_info') > +=C2=A0=C2=A0=C2=A0 bitmap =3D gdb.parse_and_eval('irq_stat_count_show') > +=C2=A0=C2=A0=C2=A0 bitsperlong =3D 8 * int(bitmap.type.target().sizeof) > =C2=A0 > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_LOCAL_APIC: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "LOC", 'apic_timer_irqs', "Local timer interrupts") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "SPU", 'irq_spurious_count', "Spurious interrupts") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "PMI", 'apic_perf_irqs', "Performance monitoring interrupts") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "IWI", 'apic_irq_work_irqs', "IRQ work interrupts") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "RTR", 'icr_read_retry_count', "APIC ICR read retries") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if utils.gdb_eval_or_none("x8= 6_platform_ipi_callback") is not None: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text = +=3D x86_show_irqstat(prec, "PLT", 'x86_platform_ipis', "Platform interrupt= s") > - > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_SMP: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "RES", 'irq_resched_count', "Rescheduling interrupts") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "CAL", 'irq_call_count', "Function call interrupts") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "TLB", 'irq_tlb_count', "TLB shootdowns") > - > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_THERMAL_VECTOR: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "TRM", 'irq_thermal_count', "Thermal events interrupts") > - > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_MCE_THRESHOLD: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "THR", 'irq_threshold_count', "Threshold APIC interrupts") > - > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_MCE_AMD: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "DFR", 'irq_deferred_error_count', "Deferred Error APIC interrupts") > - > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_MCE: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_mce(prec, = "&mce_exception_count", "MCE", "Machine check exceptions") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_mce(prec, = "&mce_poll_count", "MCP", "Machine check polls") > - > -=C2=A0=C2=A0=C2=A0 text +=3D show_irq_err_count(prec) > - > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_X86_IO_APIC: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 cnt =3D utils.gdb_eval_or_non= e("irq_mis_count") > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if cnt is not None: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text = +=3D "%*s: %10u\n" % (prec, "MIS", cnt['counter']) > - > -=C2=A0=C2=A0=C2=A0 if constants.LX_CONFIG_KVM: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "PIN", 'kvm_posted_intr_ipis', 'Posted-interrupt notification event') > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "NPI", 'kvm_posted_intr_nested_ipis', 'Nested posted-interrupt event') > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, "PIW", 'kvm_posted_intr_wakeup_ipis', 'Posted-interrupt wakeup event') > +=C2=A0=C2=A0=C2=A0 text =3D "" > +=C2=A0=C2=A0=C2=A0 for idx in range(int(info.type.sizeof / info_type.siz= eof)): > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 show =3D bitmap[int(idx / bit= sperlong)] > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if not show & 1 << int(idx % = bitsperlong): > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 conti= nue > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pfx =3D info[idx]['symbol'].s= tring() > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 desc =3D info[idx]['text'].st= ring() > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D x86_show_irqstat(pr= ec, pfx, idx, desc) > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0 return text > =C2=A0 > @@ -187,6 +145,13 @@ irq_desc_type =3D utils.CachedType("struct > =C2=A0=C2=A0=C2=A0=C2=A0 text +=3D "%*s: %10lu\n" % (prec, "ERR", gdb.par= se_and_eval("irq_err_count")) > =C2=A0=C2=A0=C2=A0=C2=A0 return text > =C2=A0 > +def show_irq_err_count(prec): > +=C2=A0=C2=A0=C2=A0 cnt =3D utils.gdb_eval_or_none("irq_err_count") > +=C2=A0=C2=A0=C2=A0 text =3D "" > +=C2=A0=C2=A0=C2=A0 if cnt is not None: > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 text +=3D "%*s: %10u\n" % (pr= ec, "ERR", cnt['counter']) > +=C2=A0=C2=A0=C2=A0 return text > + > =C2=A0def arch_show_interrupts(prec): > =C2=A0=C2=A0=C2=A0=C2=A0 text =3D "" > =C2=A0=C2=A0=C2=A0=C2=A0 if utils.is_target_arch("x86"):