From: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com>
To: gregkh@linuxfoundation.org
Cc: jirislaby@kernel.org, linux-kernel@vger.kernel.org,
Jiapeng Zhong <abaci-bugfix@linux.alibaba.com>
Subject: [PATCH v2] drivers/tty: Use bitwise instead of arithmetic operator for flags
Date: Mon, 18 Jan 2021 18:05:02 +0800 [thread overview]
Message-ID: <1610964302-73999-1-git-send-email-abaci-bugfix@linux.alibaba.com> (raw)
Fix the following coccicheck warning:
./drivers/tty/synclink_gt.c:4384:15-16: WARNING: sum of probable
bitmasks, consider |
./drivers/tty/synclink_gt.c:4342:39-40: WARNING: sum of probable
bitmasks, consider |
./drivers/tty/synclink_gt.c:4280:48-49: WARNING: sum of probable
bitmasks, consider |
./drivers/tty/synclink_gt.c:2221:20-21: WARNING: sum of probable
bitmasks, consider |
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com>
---
Changes in v2:
-Supplement and modification.
drivers/tty/synclink_gt.c | 34 ++++++++++++++++++++++++----------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/tty/synclink_gt.c b/drivers/tty/synclink_gt.c
index c0b384e..fa2a92a 100644
--- a/drivers/tty/synclink_gt.c
+++ b/drivers/tty/synclink_gt.c
@@ -2219,7 +2219,7 @@ static void isr_tdma(struct slgt_info *info)
*/
wr_reg32(info, TDCSR, status); /* clear pending */
- if (status & (BIT5 + BIT4 + BIT3)) {
+ if (status & (BIT5 | BIT4 | BIT3)) {
// another transmit buffer has completed
// run bottom half to get more send data from user
info->pending_bh |= BH_TRANSMIT;
@@ -4263,9 +4263,11 @@ static void sync_mode(struct slgt_info *info)
switch(info->params.mode) {
case MGSL_MODE_XSYNC:
- val |= BIT15 + BIT13;
+ val |= BIT15 | BIT13;
+ break;
+ case MGSL_MODE_MONOSYNC:
+ val |= BIT14 | BIT13;
break;
- case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
case MGSL_MODE_BISYNC: val |= BIT15; break;
case MGSL_MODE_RAW: val |= BIT13; break;
}
@@ -4276,17 +4278,27 @@ static void sync_mode(struct slgt_info *info)
{
case HDLC_ENCODING_NRZB: val |= BIT10; break;
case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
- case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
+ case HDLC_ENCODING_NRZI:
+ val |= BIT11 | BIT10;
+ break;
case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
- case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
- case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
- case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
+ case HDLC_ENCODING_BIPHASE_SPACE:
+ val |= BIT12 | BIT10;
+ break;
+ case HDLC_ENCODING_BIPHASE_LEVEL:
+ val |= BIT12 | BIT11;
+ break;
+ case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
+ val |= BIT12 | BIT11 | BIT10;
+ break;
}
switch (info->params.crc_type & HDLC_CRC_MASK)
{
case HDLC_CRC_16_CCITT: val |= BIT9; break;
- case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
+ case HDLC_CRC_32_CCITT:
+ val |= BIT9 | BIT8;
+ break;
}
if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
@@ -4296,7 +4308,9 @@ static void sync_mode(struct slgt_info *info)
{
case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
- case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
+ case HDLC_PREAMBLE_LENGTH_64BITS:
+ val |= BIT5 | BIT4;
+ break;
}
if (info->params.flags & HDLC_FLAG_AUTO_CTS)
@@ -4382,7 +4396,7 @@ static void sync_mode(struct slgt_info *info)
// reference clock, so take TxC from BRG/16 to get
// transmit clock at actual data rate
if (info->params.flags & HDLC_FLAG_RXC_DPLL)
- val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
+ val |= BIT6 | BIT5; /* 011, txclk = BRG/16 */
else
val |= BIT6; /* 010, txclk = BRG */
}
--
1.8.3.1
reply other threads:[~2021-01-18 21:34 UTC|newest]
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