From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA4E1C43461 for ; Mon, 12 Apr 2021 07:25:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 96C1961074 for ; Mon, 12 Apr 2021 07:25:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236881AbhDLH0E (ORCPT ); Mon, 12 Apr 2021 03:26:04 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:31248 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231274AbhDLH0C (ORCPT ); Mon, 12 Apr 2021 03:26:02 -0400 X-UUID: ea5359543a3541d181d5040e52e09060-20210412 X-UUID: ea5359543a3541d181d5040e52e09060-20210412 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 633026518; Mon, 12 Apr 2021 15:25:38 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 15:25:36 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Apr 2021 15:25:35 +0800 From: Yongqiang Niu To: Chun-Kuang Hu , Rob Herring CC: Philipp Zabel , David Airlie , Daniel Vetter , Mark Rutland , Matthias Brugger , , , , , , , Yongqiang Niu Subject: [PATCH v1] drm/mediatek: adjust rdma fifo threshold calculate formula Date: Mon, 12 Apr 2021 15:25:32 +0800 Message-ID: <1618212332-3547-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1618212332-3547-1-git-send-email-yongqiang.niu@mediatek.com> References: <1618212332-3547-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: DB7A3BFEED79B757735615E15A53186FA117C4AF185632B495D9651787FCF4D22000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org the orginal formula will caused rdma fifo threshold config overflow Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaad..8c9371b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -167,7 +167,7 @@ void mtk_rdma_config(struct device *dev, unsigned int width, * output threshold to 6 microseconds with 7/6 overhead to * account for blanking, and with a pixel depth of 4 bytes: */ - threshold = width * height * vrefresh * 4 * 7 / 1000000; + threshold = rdma_fifo_size * 7 / 10; reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); -- 1.8.1.1.dirty