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Fri, 23 Apr 2021 11:07:37 -0500 Received: from LinuxHost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2242.4 via Frontend Transport; Fri, 23 Apr 2021 11:07:27 -0500 From: Vijendar Mukunda To: , CC: , , , , , "Vijendar Mukunda" , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Daniel Vetter , Lee Jones , Evan Quan , Nirmoy Das , Deepak R Varma , "open list:RADEON and AMDGPU DRM DRIVERS" , "open list:DRM DRIVERS" , open list Subject: [PATCH 2/2] drm/amd/amdgpu: Add dwc quirk for Stoney/CZ platforms Date: Fri, 23 Apr 2021 21:54:39 +0530 Message-ID: <1619195089-29710-2-git-send-email-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1619195089-29710-1-git-send-email-Vijendar.Mukunda@amd.com> References: <1619195089-29710-1-git-send-email-Vijendar.Mukunda@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d31d9c17-a362-42a4-cc3b-08d90671ec78 X-MS-TrafficTypeDiagnostic: BN6PR12MB1729: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2512; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2021 16:07:41.6407 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d31d9c17-a362-42a4-cc3b-08d90671ec78 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1729 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a quirk DW_I2S_QUIRK_STOP_ON_SHUTDOWN for Stoney/CZ platforms. For CZ/StoneyRidge platforms, ACP DMA between ACP SRAM and I2S FIFO should be stopped before stopping I2S Controller DMA. When DMA is progressing and stop request received, while DMA transfer ongoing between ACP SRAM and I2S FIFO, Stopping I2S DMA prior to ACP DMA stop resulting ACP DMA channel stop failure. ACP DMA driver can't fix this issue due to design constraint. By setting this quirk, I2S DMA gets stopped after ACP DMA stop which will fix the ACP DMA stop failure. Signed-off-by: Vijendar Mukunda --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 38 +++++++++++---------------------- 1 file changed, 13 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index b8655ff..6866b73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -245,42 +245,30 @@ static int acp_hw_init(void *handle) goto failure; } - switch (adev->asic_type) { - case CHIP_STONEY: - i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; - break; - default: - i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; - } + i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_STOP_ON_SHUTDOWN; + if (adev->asic_type == CHIP_STONEY) + i2s_pdata[0].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; + i2s_pdata[0].cap = DWC_I2S_PLAY; i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; - switch (adev->asic_type) { - case CHIP_STONEY: - i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_COMP_PARAM1 | - DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; - break; - default: - i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_COMP_PARAM1; - } + i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_COMP_PARAM1 | + DW_I2S_QUIRK_STOP_ON_SHUTDOWN; + if (adev->asic_type == CHIP_STONEY) + i2s_pdata[1].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; i2s_pdata[1].cap = DWC_I2S_RECORD; i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; - i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; - switch (adev->asic_type) { - case CHIP_STONEY: + i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_STOP_ON_SHUTDOWN; + if (adev->asic_type == CHIP_STONEY) i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; - break; - default: - break; - } i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; -- 2.7.4