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Wed, 2 Jun 2021 11:55:52 +0000 From: Pieter Cardoen Cc: Pieter Cardoen , Russell King , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Oleksij Rempel , Robert Karszniewicz , Stefan Riedmueller , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: imx: mach-imx6ul: support ptp and rmii clock from pad Date: Wed, 2 Jun 2021 13:55:32 +0200 Message-Id: <1622634933-4098-1-git-send-email-p.cardoen@televic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622621468-17013-1-git-send-email-p.cardoen@televic.com> References: <1622621468-17013-1-git-send-email-p.cardoen@televic.com> Content-Type: text/plain X-Originating-IP: [2a02:1811:b71a:2e00:dd9:9421:9245:2349] X-ClientProxiedBy: AM0PR02CA0198.eurprd02.prod.outlook.com (2603:10a6:20b:28e::35) To PR3PR07MB8049.eurprd07.prod.outlook.com (2603:10a6:102:14c::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (2a02:1811:b71a:2e00:dd9:9421:9245:2349) by AM0PR02CA0198.eurprd02.prod.outlook.com (2603:10a6:20b:28e::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.4173.22 via Frontend Transport; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On imx6ul, the ENET RMII and PTP clock can come from either internal ANATOP/CCM or external clock source through pad ENET1_TX_CLK. But in case of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared. The patch adds the support for systems that use an external clock source and distinguishes above two cases by checking if the PTP clock specified in device tree is the one coming from the internal ANATOP/CCM. Signed-off-by: Pieter Cardoen --- arch/arm/mach-imx/mach-imx6ul.c | 44 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 35e8120..70d82cf 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -2,6 +2,7 @@ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. */ +#include #include #include #include @@ -18,14 +19,51 @@ static void __init imx6ul_enet_clk_init(void) { + struct device_node *np; + struct clk *ptp_clk; + struct clk *enet_ref; struct regmap *gpr; + u32 clksel; + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-fec"); + if (!np) { + pr_warn("%s: failed to find fec node\n", __func__); + return; + } + + ptp_clk = of_clk_get(np, 2); + if (IS_ERR(ptp_clk)) { + pr_warn("%s: failed to get ptp clock\n", __func__); + goto put_node; + } + + enet_ref = clk_get_sys(NULL, "enet_ref"); + if (IS_ERR(enet_ref)) { + pr_warn("%s: failed to get enet clock\n", __func__); + goto put_ptp_clk; + } + + /* + * If enet_ref from ANATOP/CCM is the PTP clock source, we need to + * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad + * (external OSC), and we need to clear the bit. + */ + clksel = clk_is_match(ptp_clk, enet_ref) ? + IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : + IMX6Q_GPR1_ENET_CLK_SEL_PAD; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); if (!IS_ERR(gpr)) - regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR, - IMX6UL_GPR1_ENET_CLK_OUTPUT); + regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6Q_GPR1_ENET_CLK_SEL_MASK, + clksel); else - pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n"); + pr_err("failed to find fsl,imx6ul-iomuxc-gpr regmap\n"); + + clk_put(enet_ref); +put_ptp_clk: + clk_put(ptp_clk); +put_node: + of_node_put(np); } static inline void imx6ul_enet_init(void) -- 2.7.4