From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com,
jmattson@google.com, wei.w.wang@intel.com,
like.xu.linux@gmail.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Like Xu <like.xu@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v5 01/13] perf/x86/intel: Fix the comment about guest LBR support on KVM
Date: Fri, 9 Jul 2021 18:04:59 +0800 [thread overview]
Message-ID: <1625825111-6604-2-git-send-email-weijiang.yang@intel.com> (raw)
In-Reply-To: <1625825111-6604-1-git-send-email-weijiang.yang@intel.com>
From: Like Xu <like.xu@linux.intel.com>
Starting from v5.12, KVM reports guest LBR and extra_regs support
when the host has relevant support. Just delete this part of the
comment and fix a typo incidentally.
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
arch/x86/events/intel/core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e28892270c58..84fdb8a085e5 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6249,8 +6249,7 @@ __init int intel_pmu_init(void)
x86_pmu.intel_ctrl);
/*
* Access LBR MSR may cause #GP under certain circumstances.
- * E.g. KVM doesn't support LBR MSR
- * Check all LBT MSR here.
+ * Check all LBR MSR here.
* Disable LBR access if any LBR MSRs can not be accessed.
*/
if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
--
2.21.1
next prev parent reply other threads:[~2021-07-09 9:51 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 10:04 [PATCH v5 00/13] Introduce Architectural LBR for vPMU Yang Weijiang
2021-07-09 10:04 ` Yang Weijiang [this message]
2021-07-09 10:05 ` [PATCH v5 02/13] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 03/13] KVM: x86: Add arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2021-07-09 18:24 ` Jim Mattson
2021-07-12 8:55 ` Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 04/13] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2021-07-09 20:35 ` Jim Mattson
2021-07-12 9:17 ` Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 05/13] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2021-07-09 21:55 ` Jim Mattson
2021-07-12 9:36 ` Yang Weijiang
2021-07-12 10:10 ` Like Xu
2021-07-13 9:05 ` Yang Weijiang
2021-07-10 0:42 ` kernel test robot
2021-07-09 10:05 ` [PATCH v5 06/13] KVM: x86/vmx: Save/Restore host MSR_ARCH_LBR_CTL state Yang Weijiang
2021-07-09 22:54 ` Jim Mattson
2021-07-09 23:41 ` Jim Mattson
2021-07-12 9:53 ` Yang Weijiang
2021-07-12 10:19 ` Like Xu
2021-07-12 17:20 ` Jim Mattson
2021-07-12 17:45 ` Jim Mattson
2021-07-13 9:49 ` Like Xu
2021-07-13 17:00 ` Jim Mattson
2021-07-14 13:33 ` Like Xu
2021-07-14 16:15 ` Jim Mattson
2021-07-13 9:53 ` Yang Weijiang
2021-07-12 9:50 ` Yang Weijiang
2021-07-12 17:23 ` Jim Mattson
2021-07-13 9:47 ` Yang Weijiang
2021-07-13 10:16 ` Like Xu
2021-07-13 17:12 ` Jim Mattson
2021-07-14 13:55 ` Like Xu
2021-07-09 10:05 ` [PATCH v5 07/13] KVM: x86/pmu: Refactor code to support guest Arch LBR Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 08/13] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 09/13] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 10/13] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 11/13] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 12/13] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2021-07-09 10:05 ` [PATCH v5 13/13] KVM: x86/cpuid: Advise Arch LBR feature in CPUID Yang Weijiang
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