From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
vkuznets@redhat.com, wei.w.wang@intel.com,
like.xu.linux@gmail.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Like Xu <like.xu@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v6 02/12] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
Date: Fri, 16 Jul 2021 16:49:56 +0800 [thread overview]
Message-ID: <1626425406-18582-3-git-send-email-weijiang.yang@intel.com> (raw)
In-Reply-To: <1626425406-18582-1-git-send-email-weijiang.yang@intel.com>
From: Like Xu <like.xu@linux.intel.com>
The x86_pmu.lbr_info is 0 unless explicitly initialized, so there's
no point checking x86_pmu.intel_cap.lbr_format.
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
arch/x86/events/intel/lbr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index e8453de7a964..46dc8f6cc21a 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1848,12 +1848,10 @@ void __init intel_pmu_arch_lbr_init(void)
*/
int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
{
- int lbr_fmt = x86_pmu.intel_cap.lbr_format;
-
lbr->nr = x86_pmu.lbr_nr;
lbr->from = x86_pmu.lbr_from;
lbr->to = x86_pmu.lbr_to;
- lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;
+ lbr->info = x86_pmu.lbr_info;
return 0;
}
--
2.21.1
next prev parent reply other threads:[~2021-07-16 8:38 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 8:49 [PATCH v6 00/12] Introduce Architectural LBR for vPMU Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 01/12] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2021-07-16 8:49 ` Yang Weijiang [this message]
2021-07-16 8:49 ` [PATCH v6 03/12] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 04/12] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2021-07-16 23:33 ` Jim Mattson
2021-07-19 7:27 ` Yang Weijiang
2021-07-16 8:49 ` [PATCH v6 05/12] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 06/12] KVM: x86/pmu: Refactor code to support " Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 07/12] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 08/12] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 09/12] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 10/12] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 11/12] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2021-07-16 8:50 ` [PATCH v6 12/12] KVM: x86/cpuid: Advise Arch LBR feature in CPUID Yang Weijiang
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