From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com,
like.xu.linux@gmail.com, vkuznets@redhat.com,
wei.w.wang@intel.com, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v8 14/15] KVM: x86/vmx: Flip Arch LBREn bit on guest state change
Date: Tue, 24 Aug 2021 15:56:16 +0800 [thread overview]
Message-ID: <1629791777-16430-15-git-send-email-weijiang.yang@intel.com> (raw)
In-Reply-To: <1629791777-16430-1-git-send-email-weijiang.yang@intel.com>
Per spec:"IA32_LBR_CTL.LBREn is saved and cleared on #SMI, and restored
on RSM. On a warm reset, all LBR MSRs, including IA32_LBR_DEPTH, have their
values preserved. However, IA32_LBR_CTL.LBREn is cleared to 0, disabling LBRs."
So clear Arch LBREn bit on #SMI and restore it on RSM manully, also clear the
bit when guest does warm reset.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
arch/x86/kvm/vmx/vmx.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 316403cb4038..ea1efb48d1d6 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -4519,8 +4519,10 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
vmx_update_exception_bitmap(vcpu);
vpid_sync_context(vmx->vpid);
- if (init_event)
+ if (init_event) {
vmx_clear_hlt(vcpu);
+ flip_arch_lbr_ctl(vcpu, false);
+ }
}
static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
@@ -7523,6 +7525,7 @@ static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
vmx->nested.smm.vmxon = vmx->nested.vmxon;
vmx->nested.vmxon = false;
vmx_clear_hlt(vcpu);
+ flip_arch_lbr_ctl(vcpu, false);
return 0;
}
@@ -7543,6 +7546,7 @@ static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
vmx->nested.smm.guest_mode = false;
}
+ flip_arch_lbr_ctl(vcpu, true);
return 0;
}
--
2.25.1
next prev parent reply other threads:[~2021-08-24 7:43 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-24 7:56 [PATCH v8 00/15] Introduce Architectural LBR for vPMU Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 01/15] perf/x86/intel: Fix the comment about guest LBR support on KVM Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 02/15] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 03/15] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 04/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 05/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Yang Weijiang
2021-08-25 7:59 ` kernel test robot
2021-08-27 1:06 ` kernel test robot
2021-08-24 7:56 ` [PATCH v8 06/15] KVM: x86/pmu: Refactor code to support " Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 07/15] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 08/15] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 09/15] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 10/15] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 11/15] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 12/15] KVM: nVMX: Add necessary Arch LBR settings for nested VM Yang Weijiang
2021-08-24 7:56 ` [PATCH v8 13/15] KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest Yang Weijiang
2021-08-24 7:56 ` Yang Weijiang [this message]
2021-08-24 7:56 ` [PATCH v8 15/15] KVM: x86/cpuid: Advise Arch LBR feature in CPUID Yang Weijiang
2021-10-15 0:01 ` Sean Christopherson
2021-10-15 1:28 ` Yang Weijiang
2021-10-15 2:05 ` Like Xu
2021-10-15 14:49 ` Sean Christopherson
2021-09-07 3:26 ` [PATCH v8 00/15] Introduce Architectural LBR for vPMU Yang Weijiang
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