From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3357CC433F5 for ; Fri, 17 Sep 2021 00:49:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 198B661209 for ; Fri, 17 Sep 2021 00:49:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241984AbhIQAue (ORCPT ); Thu, 16 Sep 2021 20:50:34 -0400 Received: from mail-io1-f45.google.com ([209.85.166.45]:42767 "EHLO mail-io1-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241940AbhIQAuc (ORCPT ); Thu, 16 Sep 2021 20:50:32 -0400 Received: by mail-io1-f45.google.com with SMTP id b10so10129448ioq.9; Thu, 16 Sep 2021 17:49:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:in-reply-to:references:subject:date :message-id; bh=O2spRFbCOUOnJB6jpuql0vC/edxjCzLdfxtqH2j6VJY=; b=akoeOCAhxYyq/H1IFVgR7tbJQyPFPJil1DlSfIPvV4zWRkTXnGQrlttUdgj5MIRLyJ x8an9OgrtqRX9a0/UoijksXVKbaSy4LsM5Lb9fSzm16R9WqtwjEbcI2LvJpwVFabPmeb tDWXMINWskGMeMQeLfA/ILTUrooztAorVWMkQcCJ9mSa0DYCaFFwU0gp2J0oKgtFNna4 9icVz3G39/Gul0QgGSZUJJ3NPjRNtNXdXXKrwiJPYSf0N8BafF8V+sakYdADmUfSSvIh jC5oJ/gezFy/cGoYPSvEoI2VoJXiYVXPC6ngSfTNZSiCpSrERhMfhP/s96Q9FI81OrVk qTXQ== X-Gm-Message-State: AOAM533IM4lqsoeMPpdyMA/G5EZDLMixoiJx62SQ91AmP8fIKoIFj3QS bLHH2GLk716IOAwRzUe75A== X-Google-Smtp-Source: ABdhPJzecYiE/DMtj7b8c+o0dRLsJAM1UEhGjCxttMsu3UhHMST0+ADy/DBp106ezADEWTugRBTCtw== X-Received: by 2002:a5d:8505:: with SMTP id q5mr6382635ion.53.1631839751026; Thu, 16 Sep 2021 17:49:11 -0700 (PDT) Received: from robh.at.kernel.org (96-84-70-89-static.hfc.comcastbusiness.net. [96.84.70.89]) by smtp.gmail.com with ESMTPSA id a16sm2663931ili.64.2021.09.16.17.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 17:49:10 -0700 (PDT) Received: (nullmailer pid 1484028 invoked by uid 1000); Fri, 17 Sep 2021 00:49:06 -0000 From: Rob Herring To: Sean Anderson Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Alvaro Gamez , linux-arm-kernel@lists.infradead.org, Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Thierry Reding , linux-kernel@vger.kernel.org, michal.simek@xilinx.com In-Reply-To: <20210916180544.2873770-1-sean.anderson@seco.com> References: <20210916180544.2873770-1-sean.anderson@seco.com> Subject: Re: [PATCH v7 1/3] dt-bindings: pwm: Add Xilinx AXI Timer Date: Thu, 16 Sep 2021 19:49:06 -0500 Message-Id: <1631839746.883519.1484027.nullmailer@robh.at.kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 16 Sep 2021 14:05:41 -0400, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a > "soft" block, so it has some parameters which would not be configurable in > most hardware. This binding is usually automatically generated by Xilinx's > tools, so the names and values of some properties should be kept as they > are, if possible. In addition, this binding is already in the kernel at > arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. > > The existing driver uses the clock-frequency property, or alternatively the > /cpus/timebase-frequency property as its frequency input. Because these > properties are deprecated, they have not been included with this schema. > All new bindings should use the clocks/clock-names properties to specify > the parent clock. > > Because we need to init timer devices so early in boot, we determine if we > should use the PWM driver or the clocksource/clockevent driver by the > presence/absence, respectively, of #pwm-cells. Because both counters are > used by the PWM, there is no need for a separate property specifying which > counters are to be used for the PWM. > > Signed-off-by: Sean Anderson > --- > > Changes in v7: > - Add #pwm-cells to properties > - Document why additionalProperties is true > > Changes in v6: > - Enumerate possible counter widths > - Fix incorrect schema id > > Changes in v5: > - Add example for timer binding > - Fix indentation lint > - Move schema into the timer directory > - Remove xlnx,axi-timer-2.0 compatible string > - Update commit message to reflect revisions > > Changes in v4: > - Make some properties optional for clocksource drivers > - Predicate PWM driver on the presence of #pwm-cells > - Remove references to generate polarity so this can get merged > > Changes in v3: > - Add an example with non-deprecated properties only. > - Add xlnx,pwm and xlnx,gen?-active-low properties. > - Make newer replacement properties mutually-exclusive with what they > replace > - Mark all boolean-as-int properties as deprecated > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/timer/xlnx,xps-timer.yaml | 94 +++++++++++++++++++ > 1 file changed, 94 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml:71:111: [warning] line too long (154 > 110 characters) (line-length) dtschema/dtc warnings/errors: doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1529007 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.