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Mon, 19 Aug 2024 13:23:34 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47JDNXbv014618 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 19 Aug 2024 13:23:33 GMT Received: from [10.239.97.152] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 19 Aug 2024 06:23:27 -0700 Message-ID: <1633e348-5b81-4ca6-bdb1-04bd8f81c6b8@quicinc.com> Date: Mon, 19 Aug 2024 21:23:24 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 12/13] media: qcom: camss: Add CSID Gen3 support for sm8550 To: Bryan O'Donoghue , , , , , , CC: , , , , , Yongsheng Li References: <20240812144131.369378-1-quic_depengs@quicinc.com> <20240812144131.369378-13-quic_depengs@quicinc.com> Content-Language: en-US From: Depeng Shao In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ih8nEOd881MUtb46nLxO4ChYDFqQf_OP X-Proofpoint-GUID: ih8nEOd881MUtb46nLxO4ChYDFqQf_OP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-19_11,2024-08-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 mlxlogscore=901 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408190089 Hi Bryan, On 8/16/2024 10:21 PM, Bryan O'Donoghue wrote: > On 12/08/2024 15:41, Depeng Shao wrote: >> +#define CSID_RDI_CFG1(rdi)        (0x510 + 0x100 * (rdi)) >> +#define        RDI_CFG1_DROP_H_EN        5 >> +#define        RDI_CFG1_DROP_V_EN        6 >> +#define        RDI_CFG1_CROP_H_EN        7 >> +#define        RDI_CFG1_CROP_V_EN        8 >> +#define        RDI_CFG1_PIX_STORE        10 > > Hmm - is bit 10 valid ? I'm looking at a register set derived from 8550 > and don't see it > The bit10 is valid in sm8550, but it isn't there in sm8750. >> +#define        RDI_CFG1_PACKING_FORMAT        15 > > Bit 15 selects either BIT(15) = 0 PACKING_FORMAT_PLAIN or BIT(15) = 1 > PACKING_FORMAT_MIPI > > Please give this bit a more descriptive name => > > #define        RDI_CFG1_PACKING_FORMAT_MIPI        15 > Sure. I will update it. Thanks, Depeng