From: "tip-bot2 for Jim Mattson" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Jim Mattson <jmattson@google.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/cpu] x86/cpufeatures: Put the AMX macros in the word 18 block
Date: Thu, 03 Feb 2022 20:27:32 -0000 [thread overview]
Message-ID: <164392005238.16921.14502952787568849778.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20220203194308.2469117-1-jmattson@google.com>
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: ae75fa54228162ecd65341f9780886f21f557cc4
Gitweb: https://git.kernel.org/tip/ae75fa54228162ecd65341f9780886f21f557cc4
Author: Jim Mattson <jmattson@google.com>
AuthorDate: Thu, 03 Feb 2022 11:43:07 -08:00
Committer: Dave Hansen <dave.hansen@linux.intel.com>
CommitterDate: Thu, 03 Feb 2022 12:19:39 -08:00
x86/cpufeatures: Put the AMX macros in the word 18 block
These macros are for bits in CPUID.(EAX=7,ECX=0):EDX, not for bits in
CPUID(EAX=7,ECX=1):EAX. Put them with their brethren.
Signed-off-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lkml.kernel.org/r/20220203194308.2469117-1-jmattson@google.com
---
arch/x86/include/asm/cpufeatures.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 6db4e29..4cc0ef9 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -299,9 +299,6 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
-#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
-#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
-#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
@@ -392,6 +389,9 @@
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
#define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
+#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */
+#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */
+#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
next prev parent reply other threads:[~2022-02-03 20:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-03 19:43 [PATCH 1/2] " Jim Mattson
2022-02-03 19:43 ` [PATCH 2/2] x86/cpufeatures: Add macros for Intel's new fast rep string features Jim Mattson
2022-02-03 20:25 ` Dave Hansen
2022-02-03 20:50 ` Jim Mattson
2022-02-03 20:27 ` tip-bot2 for Jim Mattson [this message]
2022-02-08 9:54 ` [tip: x86/cpu] x86/cpufeatures: Put the AMX macros in the word 18 block tip-bot2 for Jim Mattson
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