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Wed, 2 Mar 2022 00:44:01 -0800 From: Ashish Mhetre To: , , , , , , , CC: , , Subject: [Patch v4 1/4] arm64: tegra: Add memory controller channels Date: Wed, 2 Mar 2022 14:13:26 +0530 Message-ID: <1646210609-21943-2-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> References: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0932f8d7-6848-4d53-519a-08d9fc28d01c X-MS-TrafficTypeDiagnostic: BN9PR12MB5034:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ua+9wnIESBkiBj1U3y8tZOB7aRcoGGtBLzKko2xfAPNA4mT7F8P6cHd5Dv93/5/H0FmF8tjvFWNjybBDde3iuTg9ddZM9xZ1oQAvo7croAcefEiZlL1oRr7GnqtbVxIW53XQiXkQTYAXnO8nCd7RVsA5+oBcbnGYS74+sRIzjFcHjFr6gqNj27RXcyBfBmsd0weRPgDwsJbOrZLsYcoQt8rJfXjLW1XO+d5TO8thve9RchL8JF8TSnmvhohvAcH50U0axzWUXADBsG2WR47sdswIbM+wCo22Md2BN0ku6OQZ7OR1kwfcYjMtySOGWdFLV+uBsLRZnEGMZ/PNGe5ZfZOjS+ijx9E0ltg0eFsvn/QkIUNYnlutfr1SYImLU2um2yYwCpfWsUmUPuf5HzBUiSaPNYiePMEiEwWSaEBeq89zMYLt/J/6o5gRg5kwSiVWtzvG59fQJwdOftf7ZCUTeE4JFcNIds8RlanAemzUlWEDwNsRTVQs7Yuz5vFeK+nwWoSDyxa78mEobax/Mrq0+9DR1iAU8mkKAndidWpszLoRQvTEkHKa4XtFiuhOK+TF67mlRcZxABnPguxBgbPYClxXhwxHuMGwflmNyqRHVlDnJ6lFdPH0bDacNlhxmGBbX+MPwQeWAAsOCGtjlYMN/riegOZMWCxHTFXXcS4qvokuRPyIbBeogPl+sUXaMGUAR5nGEsICjRR6shfz5OWp6g== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(186003)(26005)(107886003)(426003)(336012)(40460700003)(7696005)(2906002)(2616005)(82310400004)(86362001)(36860700001)(83380400001)(47076005)(356005)(81166007)(54906003)(6666004)(5660300002)(4326008)(70206006)(8936002)(508600001)(36756003)(8676002)(70586007)(110136005)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 08:44:06.8950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0932f8d7-6848-4d53-519a-08d9fc28d01c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5034 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Signed-off-by: Ashish Mhetre --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 ++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 21 ++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 21 ++++++++++++++++++--- 3 files changed, 42 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index e9b40f5..9c14404 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -521,7 +521,12 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ interrupts = ; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c28bf4d..e19c56c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -604,9 +604,24 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ interrupts = ; #interconnect-cells = <1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace60..6e33d2b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -507,9 +507,24 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ interrupts = ; #interconnect-cells = <1>; status = "okay"; -- 2.7.4