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Wed, 2 Mar 2022 00:44:20 -0800 From: Ashish Mhetre To: , , , , , , , CC: , , Subject: [Patch v4 3/4] memory: tegra: Add memory controller channels support Date: Wed, 2 Mar 2022 14:13:28 +0530 Message-ID: <1646210609-21943-4-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> References: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6c7c4b1a-7f4f-454a-9585-08d9fc28dbc8 X-MS-TrafficTypeDiagnostic: BN8PR12MB3249:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BaS1j+ZHh3TBsVQTAUquaQx+8AjWkoCiicfpSuaVMiduzeg2NXMDCkPye/t/BY0/dAGoRFMkURaovkW3h/ZHkeaFJeSya5QzWwGWPGpNzapZjmFDFTM5kOf2SvBMMR6kAFswnXKq/zV8oAQocoUl192LgS8oUAyRZremg3lxEohNDUK726JTid0u/xL1e907eC7UYSqX4ELo/HjN8f5krT1xLKn6DGO/MGHYS1DYhnvUbs7rZjgIsEgdOSfVuDp9SQWcGkgStBI8PiFim8RWwHSHsF1SyU2IIAowpbutQU20pF17rklz7EjtpEOij4JPZovynTBAQqXx795Gpo6VB+Mg/xmrC6HxoCGHLfZM52FA0vLSteiuzEVwqO2lPj4YrJjxSOeP5Pyxp/vh7ZvQLpng5KhLT+3T3UK+k/2RcJYGpRbA/UR5F+pHa230xUnxlMuhFSKsQEhHCjccH2CDnOq4n4ASrSuf323vk3P+oYqOC9xgwYyk4e2hbgvYjrwWQ9tJVGh07sLkBXSWfHPag9f9bKKuJAuXMEz2ab40WidDeLCJECz1YBzJCwv1k/5451kcyLud+CjoU2/VFfNnV93C/6GJM9NkrNnvt9a2FmojInmYN47KuIUX2vbPr0wfH3Ko4GRGLw7CukhUq3CNaYn+rMmA4Vw+eibm2hYenwPhzbXg+pQfch/Ri2OEJPNgSRFTAYMezgjzDZxPuYM7BA== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(5660300002)(426003)(7696005)(336012)(47076005)(81166007)(107886003)(356005)(36756003)(83380400001)(2616005)(2906002)(40460700003)(26005)(186003)(110136005)(54906003)(70206006)(8676002)(86362001)(4326008)(8936002)(70586007)(82310400004)(36860700001)(508600001)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 08:44:26.4633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c7c4b1a-7f4f-454a-9585-08d9fc28dbc8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3249 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >From tegra186 onwards, memory controller support multiple channels. Add support for mapping address spaces of these channels. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.c | 6 ++++++ drivers/memory/tegra/tegra186.c | 21 +++++++++++++++++++++ drivers/memory/tegra/tegra194.c | 1 + drivers/memory/tegra/tegra234.c | 1 + include/soc/tegra/mc.h | 7 +++++++ 5 files changed, 36 insertions(+) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index bf3abb6..3cda1d9 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device *pdev) if (IS_ERR(mc->regs)) return PTR_ERR(mc->regs); + if (mc->soc->ops && mc->soc->ops->map_regs) { + err = mc->soc->ops->map_regs(mc, pdev); + if (err < 0) + return err; + } + mc->debugfs.root = debugfs_create_dir("mc", NULL); if (mc->soc->ops && mc->soc->ops->probe) { diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 3d15388..59a4425 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -139,11 +139,31 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) return 0; } +static int tegra186_mc_map_regs(struct tegra_mc *mc, + struct platform_device *pdev) +{ + struct resource *res; + int i; + + mc->mcb_regs = devm_platform_get_and_ioremap_resource(pdev, 1, &res); + if (IS_ERR(mc->mcb_regs)) + return PTR_ERR(mc->mcb_regs); + + for (i = 0; i < mc->soc->num_channels; i++) { + mc->mc_regs[i] = devm_platform_get_and_ioremap_resource(pdev, i + 2, &res); + if (IS_ERR(mc->mc_regs[i])) + return PTR_ERR(mc->mc_regs[i]); + } + + return 0; +} + const struct tegra_mc_ops tegra186_mc_ops = { .probe = tegra186_mc_probe, .remove = tegra186_mc_remove, .resume = tegra186_mc_resume, .probe_device = tegra186_mc_probe_device, + .map_regs = tegra186_mc_map_regs, }; #if defined(CONFIG_ARCH_TEGRA_186_SOC) @@ -875,6 +895,7 @@ const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, .num_address_bits = 40, + .num_channels = 4, .ops = &tegra186_mc_ops, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index cab998b..9400117 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1347,5 +1347,6 @@ const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index e22824a..6335a13 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -97,5 +97,6 @@ const struct tegra_mc_soc tegra234_mc_soc = { .num_clients = ARRAY_SIZE(tegra234_mc_clients), .clients = tegra234_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1066b11..92f810c 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -13,6 +13,9 @@ #include #include #include +#include + +#define MC_MAX_CHANNELS 16 struct clk; struct device; @@ -181,6 +184,7 @@ struct tegra_mc_ops { int (*resume)(struct tegra_mc *mc); irqreturn_t (*handle_irq)(int irq, void *data); int (*probe_device)(struct tegra_mc *mc, struct device *dev); + int (*map_regs)(struct tegra_mc *mc, struct platform_device *pdev); }; struct tegra_mc_soc { @@ -194,6 +198,7 @@ struct tegra_mc_soc { unsigned int atom_size; u8 client_id_mask; + u8 num_channels; const struct tegra_smmu_soc *smmu; @@ -212,6 +217,8 @@ struct tegra_mc { struct tegra_smmu *smmu; struct gart_device *gart; void __iomem *regs; + void __iomem *mcb_regs; + void __iomem *mc_regs[MC_MAX_CHANNELS]; struct clk *clk; int irq; -- 2.7.4