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Tue, 03 Mar 2026 10:15:35 -0800 (PST) X-Received: by 2002:a17:90b:3dd0:b0:359:9224:6c16 with SMTP id 98e67ed59e1d1-35992246da0mr6103119a91.14.1772561734500; Tue, 03 Mar 2026 10:15:34 -0800 (PST) Received: from [192.168.0.172] ([49.205.248.49]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3599c39def7sm2866240a91.12.2026.03.03.10.15.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2026 10:15:34 -0800 (PST) Message-ID: <164928f6-cd29-49e4-8b5e-365f5b0a70e5@oss.qualcomm.com> Date: Tue, 3 Mar 2026 23:45:25 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/7] media: iris: switch to hardware mode after firmware boot To: Konrad Dybcio , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Saravana Kannan , Joerg Roedel , Will Deacon , Robin Murphy , Stefan Schmidt , Hans Verkuil , Krzysztof Kozlowski , Vishnu Reddy , Hans Verkuil Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Bryan O'Donoghue References: <20260227-kaanapali-iris-v2-0-850043ac3933@oss.qualcomm.com> <20260227-kaanapali-iris-v2-2-850043ac3933@oss.qualcomm.com> <6fe3a1a8-46c7-427c-abb5-2e7366a43392@oss.qualcomm.com> Content-Language: en-US From: Vikash Garodia In-Reply-To: <6fe3a1a8-46c7-427c-abb5-2e7366a43392@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDE0NyBTYWx0ZWRfXyHOjvRwNNMcD wQZV+66X9wQMnT+AmzbA0b1Pt/J6aKgsmT0xlfXB9CiPsFicVDNr4QU929Dk0v/JWp6RLsWhs0+ oCLeDEVZhNlrf37rC0rCKwy1dwI66pEliE27jq59nbweHTBRrYEMnX49NvtmshTcQRz5jExHCtx 2tnIzUBizvPSmXVinHiePz06RFSDC8Z8HE2OzU+ygPYlwz3f3vFSCAOC6PlReHERn8TubL0cf52 AmPb3DP7ImhcQCpAMzLtLySm2u8IIbLRfmQReTEk7uj70z8AMJWHoViweYQSSkA9O7TwmAW3HvI bhcNUUZEKYOWVn0r+76PQQVQfdb6VeJ3he7Ib4sIm8+USvAJZZyunIpmRW9N58iPA0wzLoUbtwA gRPGCModBEOAGye24zpaWwd/yk12B1+zCzWTD/TkLmYI0yr1NdNSrO5S0vdteS9Vhkyq5z2tW26 ZrJBX+CX0r+4p30G/Ng== X-Proofpoint-ORIG-GUID: c0R0HhN40AjKYCMp3dWBUZf_T69ZeyhI X-Authority-Analysis: v=2.4 cv=S+HUAYsP c=1 sm=1 tr=0 ts=69a72548 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=KPiuay1jFzAquJblYynD6w==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=UfkxKPkKiOspLhQzxRwA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: c0R0HhN40AjKYCMp3dWBUZf_T69ZeyhI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-03_02,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030147 On 2/27/2026 10:19 PM, Konrad Dybcio wrote: > On 2/27/26 3:11 PM, Vikash Garodia wrote: >> Currently the driver switches the vcodec GDSC to hardware (HW) mode >> before firmware load and boot sequence. GDSC can be powered off, keeping >> in hw mode, thereby the vcodec registers programmed in TrustZone (TZ) >> carry default (reset) values. >> Move the transition to HW mode after firmware load and boot sequence. >> >> The bug was exposed with driver configuring different stream ids to >> different devices via iommu-map. With registers carrying reset values, >> VPU would not generate desired stream-id, thereby leading to SMMU fault. >> >> For vpu4, when GDSC is switched to HW mode, there is a need to perform >> the reset operation. Without reset, there are occassional issues of >> register corruption observed. Hence the vpu GDSC switch also involves >> the reset. > > Is that a characteristic of the hardware (e.g. also seen downstream), or > is that required with upstream iris only? it was found lately with one of vpu4 variant SOC and applicable for all vpu4s. > > Konrad Regards, Vikash