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Thu, 27 Feb 2020 21:20:30 +0000 Subject: Re: [PATCH v2 3/3] perf vendor events amd: update Zen1 events to V2 To: Vijay Thakkar Cc: Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Alexander Shishkin , Jiri Olsa , Namhyung Kim , =?UTF-8?Q?Martin_Li=c5=a1ka?= , Jon Grimm , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20200225192815.50388-1-vijaythakkar@me.com> <20200225192815.50388-4-vijaythakkar@me.com> <73b5b731-9597-1243-485a-788437500c7a@amd.com> <20200227200026.GA8493@shwetrath.localdomain> From: Kim Phillips Message-ID: <164d3a93-c607-2bd4-c9a3-dc4d8b275d42@amd.com> Date: Thu, 27 Feb 2020 15:20:29 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 In-Reply-To: <20200227200026.GA8493@shwetrath.localdomain> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN4PR0501CA0040.namprd05.prod.outlook.com (2603:10b6:803:41::17) To SN6PR12MB2845.namprd12.prod.outlook.com (2603:10b6:805:75::33) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.236.136.247] (165.204.77.1) by SN4PR0501CA0040.namprd05.prod.outlook.com (2603:10b6:803:41::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2793.5 via Frontend Transport; Thu, 27 Feb 2020 21:20:30 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 17e0c052-012c-48fe-e5f6-08d7bbcadf86 X-MS-TrafficTypeDiagnostic: SN6PR12MB2688:|SN6PR12MB2688: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 03264AEA72 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(376002)(396003)(346002)(366004)(39860400002)(136003)(199004)(189003)(956004)(52116002)(54906003)(2616005)(6916009)(44832011)(66476007)(66946007)(31686004)(66556008)(53546011)(5660300002)(2906002)(966005)(86362001)(4326008)(31696002)(36756003)(478600001)(81156014)(7416002)(186003)(16526019)(8676002)(316002)(6486002)(16576012)(26005)(8936002)(81166006);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2688;H:SN6PR12MB2845.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: y6/zwTAd6khStm7YJvOn2j8CoFBSKSEv3lKRXLPf/EM5RKxdsrgej8EDWaj3a8AvC77Cn5Ticr3OGfHy/HK6dEEstr7Dlx5G0VQwntcBB3agfUQyHbsjAKUk148Y3bVG6Bcabf6guJ0iVvFxx2gvJt76xNW2llPGM/i2EK1ybUHiMzaD2eN1PlT85WkUzuYXoNg8xCWmszTHgTauzAa+a4WXN5DKCToi3w1qCcnEdzT53F7r4VU/mM9mgm0/Ek8ed2pJIpF6EFNuPxpVwvrcKnwvsyo7VL2PWKmoZs0Yc73VxWDnJO94yRHCmGA2EE4uiPzqHYQECLeRcd11QABh2Uz9FD0/fq/SLZjaOlHtUm56UsnlHecMofK9sKlRt59qQMPDNRq/TWM0Po8kMItOj4mxbPbSkvJBoW3ZgDYDvaPZtFnY7tq8v1yCi1mHGLvkxihsTRXWTOTDWwggJx10e+2RYvaZrYKuF9BSqHEBlwhUawew33uvXhz4km5F9EG6U0ha8YFZJURz87nVOl1Yaw== X-MS-Exchange-AntiSpam-MessageData: 4qYdMT5KLVRzccxKz9ZczAUzlpWEj+0vm3QbyLiHL/kIgGcSbAQFdwGvmJiCRbpZU6lIam44AfeAx963+riGCpkCBaT3IvbLJEz8UVNLNbWE4i0kWRqhxqstMJk3bdNsYzFwZHhxyPGKojmKXsMB8w== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 17e0c052-012c-48fe-e5f6-08d7bbcadf86 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2020 21:20:30.6341 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: W8ALZPtbX5solri4qGDXM0bTpjIV34wQWsdZTPmROk5z4NVEyilIv6liBadP4gVV27MA6/dBrbZdhA5gR4Cz6Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/27/20 2:00 PM, Vijay Thakkar wrote: >> OSRR for AMD Family 17h processors, Models 00h-2Fh, 56255 Rev 3.03 - July, 2018 > I have included this for v3 that I will submit later, including all the > changes for the FPU counters. Sorry, I messed up copy-pasting the text > and forgot to change the trailing pipe number. Please also look at addressing the review comments for patch 2 of 3. >> and their counts don't seem to match up very well when running >> various workloads. The microarchitecture is likely to have changed >> in this area from families prior to 17h, so a MAB alloc can likely >> count different events than what is presumed here: a Data cache >> load/store/prefetch miss. >> >> I think it's safer to just leave the PPR text "LS MAB Allocates >> by Type" as-is, instead of assuming they are L1 load/store misses. >> What do you think? > > I did some checking accross PPRs, and this counter seems to have changed > names multiple times throughout the PPR revisions. > > Zen1 PPR (54945 Rev 1.14 - April 15, 2017) lists counter called "LsMabAllocPipe" > with 5 subcounters that have different names compared to ones we see in > the mainline right now. PPRs for stepping B2 > onwards change this to the 3 sub-counter and primary counter name > we see right now. This public description still changes accross various > PPR revisions, which is why I had this set to what it was. The lastest > PPR I can find is indeed lists it as "LS MAB Allocates by Type"; > I will change it to that with the fuffix of tehe sub-counter name. Since > the same counter is in Zen2 as well, I will make the same changes there > too. Thanks, yes, and if you look at the Software Optimization Guide that I just added to the bugzilla [1], Figure 7 "Load-Store Unit" on page 40 shows a MAB block separate from the Data Cache block. Kim [1] https://bugzilla.kernel.org/show_bug.cgi?id=206537