From: "tip-bot2 for Sandipan Das" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Sandipan Das <sandipan.das@amd.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: perf/core] x86/msr: Add PerfCntrGlobal* registers
Date: Wed, 04 May 2022 09:23:24 -0000 [thread overview]
Message-ID: <165165620446.4207.5734722623404646306.tip-bot2@tip-bot2> (raw)
In-Reply-To: =?utf-8?q?=3Ccdc0d8f75bd519848731b5c64d924f5a0619a573=2E16505?= =?utf-8?q?15382=2Egit=2Esandipan=2Edas=40amd=2Ecom=3E?=
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 089be16d5992dd0bc6df15ef12042fd1023ded9a
Gitweb: https://git.kernel.org/tip/089be16d5992dd0bc6df15ef12042fd1023ded9a
Author: Sandipan Das <sandipan.das@amd.com>
AuthorDate: Thu, 21 Apr 2022 11:16:54 +05:30
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Wed, 04 May 2022 11:18:26 +02:00
x86/msr: Add PerfCntrGlobal* registers
Add MSR definitions that will be used to enable the new AMD
Performance Monitoring Version 2 (PerfMonV2) features. These
include:
* Performance Counter Global Control (PerfCntrGlobalCtl)
* Performance Counter Global Status (PerfCntrGlobalStatus)
* Performance Counter Global Status Clear (PerfCntrGlobalStatusClr)
The new Performance Counter Global Control and Status MSRs
provide an interface for enabling or disabling multiple
counters at the same time and for testing overflow without
probing the individual registers for each PMC.
The availability of these registers is indicated through the
PerfMonV2 feature bit of CPUID leaf 0x80000022 EAX.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/cdc0d8f75bd519848731b5c64d924f5a0619a573.1650515382.git.sandipan.das@amd.com
---
arch/x86/include/asm/msr-index.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 8179ea3..58a44dc 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -524,6 +524,11 @@
#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
+/* AMD Performance Counter Global Status and Control MSRs */
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
+#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
+
/* Fam 17h MSRs */
#define MSR_F17H_IRPERF 0xc00000e9
next reply other threads:[~2022-05-04 9:24 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-04 9:23 tip-bot2 for Sandipan Das [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-04-29 20:28 tip-bot2 for Sandipan Das
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