From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5E8EC433EF for ; Thu, 30 Jun 2022 05:54:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232564AbiF3Fyf (ORCPT ); Thu, 30 Jun 2022 01:54:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232334AbiF3FyY (ORCPT ); Thu, 30 Jun 2022 01:54:24 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CE322DAA2; Wed, 29 Jun 2022 22:54:21 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C6A4E1A06F8; Thu, 30 Jun 2022 07:54:19 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 89EC41A09D2; Thu, 30 Jun 2022 07:54:19 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 27D57180222C; Thu, 30 Jun 2022 13:54:18 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock source Date: Thu, 30 Jun 2022 13:39:14 +0800 Message-Id: <1656567554-32122-7-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656567554-32122-1-git-send-email-shengjiu.wang@nxp.com> References: <1656567554-32122-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add two PLL clock source, they are the parent clocks of root clock one is for 8kHz series rates, another one is for 11kHz series rates. They are optional clocks, if there are such clocks, then driver can switch between them for supporting more accurate rates. Signed-off-by: Shengjiu Wang --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 4c66e6a1a533..fbdefc3fade7 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -21,6 +21,9 @@ Required properties: - clock-names : Must include the "bus" for register access and "mclk1", "mclk2", "mclk3" for bit clock and frame clock providing. + "pll8k", "pll11k" are optional, they are the clock + source for root clock, one is for 8kHz series rates + another one is for 11kHz series rates. - dmas : Generic dma devicetree binding as described in Documentation/devicetree/bindings/dma/dma.txt. -- 2.17.1