From: Conor Dooley <mail@conchuod.ie>
To: conor.dooley@microchip.com, daire.mcnamara@microchip.com
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, broonie@kernel.org,
nagasuresh.relli@microchip.com,
valentina.fernandezalanis@microchip.com,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH] riscv: dts: microchip: add qspi compatible fallback
Date: Mon, 15 Aug 2022 21:29:37 +0100 [thread overview]
Message-ID: <166059535262.2709508.15329793193826864091.b4-ty@microchip.com> (raw)
In-Reply-To: <20220810085914.801170-1-conor.dooley@microchip.com>
From: Conor Dooley <conor.dooley@microchip.com>
On Wed, 10 Aug 2022 09:59:15 +0100, Conor Dooley wrote:
> The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
> of the FPGA IP core. The original binding had no fallback etc, so this
> device tree is valid as is. There was also no functional driver for the
> QSPI IP, so no device with a devicetree from a previous mainline
> release will regress.
>
>
> [...]
Applied to dt-for-next, thanks!
[1/1] riscv: dts: microchip: add qspi compatible fallback
https://git.kernel.org/conor/c/7eac0081a8e9
Thanks,
Conor.
prev parent reply other threads:[~2022-08-16 0:19 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-10 8:59 Conor Dooley
2022-08-10 13:29 ` Krzysztof Kozlowski
2022-08-15 20:29 ` Conor Dooley [this message]
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