From: Will Deacon <will@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
James Morse <james.morse@arm.com>,
Ionela Voinescu <ionela.voinescu@arm.com>
Cc: kernel-team@android.com, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly
Date: Tue, 23 Aug 2022 12:34:18 +0100 [thread overview]
Message-ID: <166124920909.3125510.14641802856541265933.b4-ty@kernel.org> (raw)
In-Reply-To: <20220819103050.24211-1-ionela.voinescu@arm.com>
On Fri, 19 Aug 2022 11:30:50 +0100, Ionela Voinescu wrote:
> The AMU counter AMEVCNTR01 (constant counter) should increment at the same
> rate as the system counter. On affected Cortex-A510 cores, AMEVCNTR01
> increments incorrectly giving a significantly higher output value. This
> results in inaccurate task scheduler utilization tracking and incorrect
> feedback on CPU frequency.
>
> Work around this problem by returning 0 when reading the affected counter
> in key locations that results in disabling all users of this counter from
> using it either for frequency invariance or as FFH reference counter. This
> effect is the same to firmware disabling affected counters.
>
> [...]
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly
https://git.kernel.org/arm64/c/e89d120c4b72
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
prev parent reply other threads:[~2022-08-23 15:05 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-19 10:30 Ionela Voinescu
2022-08-23 11:34 ` Will Deacon [this message]
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