From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF877C433F5 for ; Thu, 29 Sep 2022 10:21:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235038AbiI2KVU (ORCPT ); Thu, 29 Sep 2022 06:21:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234630AbiI2KVF (ORCPT ); Thu, 29 Sep 2022 06:21:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 311415209D for ; Thu, 29 Sep 2022 03:21:03 -0700 (PDT) Date: Thu, 29 Sep 2022 10:21:00 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1664446861; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dsxxoZaF18dNd+r0YNsoInNXPabb5v1nGksJW2WQVrI=; b=wEYIibRMpTH4xj2PTqe5gUZz9Mtx1lbehy/SMAKEGMzL8jm8zed4xw4z71QVL1raausyTE WSF7jtVdQyab9gDYPtHsfPnB/TD0zE+h0/GCGGw3pJ4KzcJ0iqH72tqrD9q155+maAD4jM a8iVKUgaF8pt3s4LwB2Sg65x3J/j34M0VKuirU7aO89isPklfdlMLK2Ca0x0f4rtjSxlWo UWurApxZcNWLZ4N3++UktJUQBJyKIiCJY22LD1zLdNNK5Np/OBJI0twKCPymdVR4nH1da3 r/yl11QaA6DAwD7+v1B7pygyVgb/xl6lL6Ds6FAwuZedF8lJDofClRZcbpQxUg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1664446861; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dsxxoZaF18dNd+r0YNsoInNXPabb5v1nGksJW2WQVrI=; b=x72iiN1WqPa/b0uKBW1OwaclDzPtVDsimWDtZc7A+gTC4d/NVt2tERUL0f7J3pg5SJ6qQZ jel2EE1/bYib2FAg== From: "irqchip-bot for Apurva Nandan" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller: ti,sci-intr: Fix missing reg property in the binding Cc: Apurva Nandan , Rob Herring , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220819190729.32358-4-a-nandan@ti.com> References: <20220819190729.32358-4-a-nandan@ti.com> MIME-Version: 1.0 Message-ID: <166444686053.401.11179384254910309532.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: daa0b6d0187599a574cb5cb392b259bda3dcf979 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/daa0b6d0187599a574cb5cb392b259bda3dcf979 Author: Apurva Nandan AuthorDate: Sat, 20 Aug 2022 00:37:29 +05:30 Committer: Marc Zyngier CommitterDate: Thu, 29 Sep 2022 11:13:43 +01:00 dt-bindings: interrupt-controller: ti,sci-intr: Fix missing reg property in the binding Fix the following warning in dtbs_check interrupt-controller@a00000: Unevaluated properties are not allowed ('reg' was unexpected) Add the reg property in the schema. Signed-off-by: Apurva Nandan Acked-by: Rob Herring Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220819190729.32358-4-a-nandan@ti.com --- Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml index e12aee4..c99cc73 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml @@ -58,6 +58,9 @@ properties: 1 = If intr supports edge triggered interrupts. 4 = If intr supports level triggered interrupts. + reg: + maxItems: 1 + interrupt-controller: true '#interrupt-cells':