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Tue, 8 Nov 2022 22:17:33 -0800 From: Kartik To: , , , , , , , , , , , Subject: [PATCH] soc/tegra: fuse: use platform info with soc revision Date: Wed, 9 Nov 2022 11:47:31 +0530 Message-ID: <1667974651-10893-1-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT033:EE_|DM4PR12MB6398:EE_ X-MS-Office365-Filtering-Correlation-Id: 6357ba5d-b77e-43cc-5d3c-08dac21a1fa1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EirPi1bdh64xMGcrPwXRpHLX/CNmSfp97XzYgjgb8FT9zChXFVbJ2Dr630Ni8Jtw2aBxLtHi+ekU08Ipyaq84TMObm0Y1pmLo84QUFUaGbfZlfA2PUZu8/v600p/G5miluTx/tPbua7vuAQooofE+v5ogQur4DYr1CulcwrYuTmqxfxdUvictcY0E2vNDbyvP8GtLW8ZnWdJK4+3MJ90Gu5lutGtHORKzijcz2Lvevil0oIvska4sgrZQqSwjhHudEcb5a5YUWm2sjJTmKluavlQqbw1d9bWOmtBR2v2WazJ5fMKyYew3xY1yl9Wy/fV9RWRHP6dBrF+So/v/QJgG8kZPEKdbWr3suTWfDbTNspyswJUeR213dJNv/2RgB8JbbX58IvaP/ZssEDuhzDA8xlT45TNeexwPHMkJyw7QUNXFhkd0hy1mBXHwUPhJP1w027oEfIQhUwzW4xW9J7hfhTM4j0WbXhsC6iFi4iHf4Jqw9eYcCGUJF4bTdi5xpEZmLgVNMFMFNETjuWAnPQJwct2Ee0EM+b6VpapxjAH2xK0HHe2Y9gzkB6Og+Zrd8l1+lfy0FY76IsA3flLOBN8PQiUl8+SaJ5sHLXVdcQXtWX9sNsULYX3US6PMmGM67NGhvRpQu2mJi5qxPUd/1V+xh0UPPlYmW8rnFFgwGo6/D25BNHc5p8AoTHds1THTeZdRlOYOdDlKB8AYJt7uW1YrBrCvtutCYPSZqhEpNXpcLXSiKCaZXBStTiLkdJT7SGu7YPdUh2h6iDMoK4sp29olFVhq7iFXPALbeZAfIyr3nY= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(136003)(376002)(396003)(451199015)(36840700001)(46966006)(40470700004)(82310400005)(478600001)(7636003)(110136005)(921005)(356005)(316002)(7696005)(47076005)(2906002)(40480700001)(26005)(8676002)(70586007)(70206006)(82740400003)(86362001)(2616005)(36756003)(8936002)(41300700001)(5660300002)(186003)(83380400001)(426003)(40460700003)(336012)(36860700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 06:17:48.0859 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6357ba5d-b77e-43cc-5d3c-08dac21a1fa1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6398 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra pre-silicon platforms does not have chip revisions. This makes "revision" soc attribute obsolete on these platforms. Populate "revision" soc attribute with "platform name + chip revision" for Silicon. For pre-silicon platforms populate it with "platform name" instead. Signed-off-by: Kartik --- drivers/soc/tegra/fuse/fuse-tegra.c | 23 +++++++++++++++++++++-- drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 + include/soc/tegra/fuse.h | 15 +++++++++++++++ 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index ea25a1dcafc2..a20c9e0105dc 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -35,6 +35,19 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { [TEGRA_REVISION_A04] = "A04", }; +static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = { + [TEGRA_PLATFORM_SILICON] = "Silicon", + [TEGRA_PLATFORM_QT] = "QT", + [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA", + [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA", + [TEGRA_PLATFORM_ASIM_QT] = "Asim QT", + [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim", + [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim", + [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation", + [TEGRA_PLATFORM_VDK] = "VDK", + [TEGRA_PLATFORM_VSP] = "VSP", +}; + static const struct of_device_id car_match[] __initconst = { { .compatible = "nvidia,tegra20-car", }, { .compatible = "nvidia,tegra30-car", }, @@ -370,8 +383,14 @@ struct device * __init tegra_soc_device_register(void) return NULL; attr->family = kasprintf(GFP_KERNEL, "Tegra"); - attr->revision = kasprintf(GFP_KERNEL, "%s", - tegra_revision_name[tegra_sku_info.revision]); + if (tegra_is_silicon()) { + attr->revision = kasprintf(GFP_KERNEL, "%s %s", + tegra_platform_name[tegra_sku_info.platform], + tegra_revision_name[tegra_sku_info.revision]); + } else { + attr->revision = kasprintf(GFP_KERNEL, "%s", + tegra_platform_name[tegra_sku_info.platform]); + } attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); attr->custom_attr_group = fuse->soc->soc_attr_group; diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 3351bd872ab2..4591c5bcb690 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -156,6 +156,7 @@ void __init tegra_init_revision(void) } tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); + tegra_sku_info.platform = tegra_get_platform(); } void __init tegra_init_apbmisc(void) diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 977c334136e9..a63de5da8124 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -34,6 +34,20 @@ enum tegra_revision { TEGRA_REVISION_MAX, }; +enum tegra_platform { + TEGRA_PLATFORM_SILICON = 0, + TEGRA_PLATFORM_QT, + TEGRA_PLATFORM_SYSTEM_FPGA, + TEGRA_PLATFORM_UNIT_FPGA, + TEGRA_PLATFORM_ASIM_QT, + TEGRA_PLATFORM_ASIM_LINSIM, + TEGRA_PLATFORM_DSIM_ASIM_LINSIM, + TEGRA_PLATFORM_VERIFICATION_SIMULATION, + TEGRA_PLATFORM_VDK, + TEGRA_PLATFORM_VSP, + TEGRA_PLATFORM_MAX, +}; + struct tegra_sku_info { int sku_id; int cpu_process_id; @@ -47,6 +61,7 @@ struct tegra_sku_info { int gpu_speedo_id; int gpu_speedo_value; enum tegra_revision revision; + enum tegra_platform platform; }; #ifdef CONFIG_ARCH_TEGRA -- 2.17.1