From: Rob Herring <robh@kernel.org>
To: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Cc: krzysztof.kozlowski@linaro.org, michals@xilinx.com,
linux-pci@vger.kernel.org, bhelgaas@google.com,
bharat.kumar.gogada@amd.com, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, devicetree@vger.kernel.org,
nagaradhesh.yeleswarapu@amd.com
Subject: Re: [PATCH v6 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge
Date: Fri, 11 Nov 2022 12:29:05 -0600 [thread overview]
Message-ID: <166819134102.3650802.6455003560050534177.robh@kernel.org> (raw)
In-Reply-To: <20221111053709.1474323-2-thippeswamy.havalige@amd.com>
On Fri, 11 Nov 2022 11:07:09 +0530, Thippeswamy Havalige wrote:
> Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
> dt binding.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> ---
> changes in v6:
> Added maxItems to clocks property.
>
> .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------
> .../bindings/pci/xlnx,nwl-pcie.yaml | 149 ++++++++++++++++++
> 2 files changed, 149 insertions(+), 73 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>
Applied, thanks!
next prev parent reply other threads:[~2022-11-11 18:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 5:37 [PATCH v6 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI " Thippeswamy Havalige
2022-11-11 5:37 ` [PATCH v6 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL " Thippeswamy Havalige
2022-11-11 7:52 ` Krzysztof Kozlowski
2022-11-11 18:29 ` Rob Herring [this message]
2022-11-11 18:28 ` [PATCH v6 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI " Rob Herring
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